ZLF645E0H2864G Zilog, ZLF645E0H2864G Datasheet - Page 150

• Manufacturer Part Number: ZLF645E0H2864G
• Description: IC MCU 64K FLASH 1K RAM 28-SSOP
• Manufacturer: Zilog
• Series: Crimzon™ ZLFr

Specifications of ZLF645E0H2864G

• Core Processor: Z8 LXMC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.9 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Oscillator Type: -
• Other names: 269-4719

PS026407-0408
Bit Position
[1]
[0]
SMR1 Register Events
The SMR1 register can be used to configure one or more Port 2 pins to be compared with
a written or sampled reference value and generate a Stop Mode Recovery event when the
pin state differs from the reference value.
To configure a Port 2 pin as an SMR1 event source, ensure it is configured as an input in
the P2M register, then set the corresponding SMR1 register bit. By default, a Stop Mode
Recovery event occurs when the pin’s state is zero.
After a Port 2 pin is configured as an SMR1 source, any subsequent read from or write to
the P2 register latches the read or write value for reference. A Stop Mode Recovery event
occurs when the pin’s state differs from the last reference value latched. The SMR1 source
logic is displayed in
The program can read register bits SMR4[1:0] to determine whether the Port 2 pins trigger
a Stop Mode Recovery on a change from the last read value (SMR4[1:0]=01), or on a
change from the last written value (SMR4[1:0]=10). Software can clear SMR4[1:0] to 00
to restore the default behavior (configured pins trigger when their state is 0). The SMR1
register is summarized in
Value Description
0
1
0
1
SMR Short Reset Time —Controls whether the devices SMR reset period is
equivalent to the RC oscillator based POR reset period or whether it depends on
the detection of XTAL1 clock oscillation.
Unless SMR[5]=1, the SMR reset period is equivalent to the devices
RC oscillator based POR reset period and falls in the range of 2.5 ms to 10 ms.
Unless SMR[5]=1, the SMR reset period falls in a range of a minimum of 2.5 ms
from chip power up or a maximum of 2.5 ms from when the XTAL1 clock reaches
a peak-to-peak amplitude of oscillation greater than 250 mV.
SCLK/TCLK Divide-by-16 Select —Controls a divide-by-16 prescaler of the
internal SCLK/TCLK signal (see
page 130). A power-on reset or Stop Mode Recovery clears this bit to 0.
Off.
On.
Figure 45
Table 71
on page 144.
on page 145.
Internal Clock Signals (SCLK and TCLK)
ZLF645 Series Flash MCUs
Reset/Stop Mode Recovery Status
Product Specification
on
142