MC68HC705C9ACP Freescale Semiconductor, MC68HC705C9ACP Datasheet - Page 53

• Manufacturer Part Number: MC68HC705C9ACP
• Description: IC MCU 2.1MHZ 16K OTP 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C9ACP

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 352 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

8.3.1 Timer Control Register
The timer control register (TCR), shown in
ICIE — Input Capture Interrupt Enable Bit
OCIE — Output Compare Interrupt Enable Bit
TOIE — Timer Overflow Interrupt Enable Bit
IEDG — Input Edge Bit
OLVL — Output Level Bit
Freescale Semiconductor
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This read/write bit enables interrupts caused by an active signal on the TCAP pin. Resets clear the
ICIE bit.
This read/write bit enables interrupts caused by an active signal on the TCMP pin. Resets clear the
OCIE bit.
This read/write bit enables interrupts caused by a timer overflow. Reset clear the TOIE bit.
The state of this read/write bit determines whether a positive or negative transition on the TCAP pin
triggers a transfer of the contents of the timer register to the input capture register. Resets have no
effect on the IEDG bit.
The state of this read/write bit determines whether a logic 1 or logic 0 appears on the TCMP pin when
a successful output compare occurs. Resets clear the OLVL bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
1 = Positive edge (low to high transition) triggers input capture
0 = Negative edge (high to low transition) triggers input capture
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
Enables input capture interrupts
Enables output compare interrupts
Enables timer overflow interrupts
Controls the active edge polarity of the TCAP signal
Controls the active level of the TCMP output
Reset:
$0012
Read:
Write:
Bit 7
ICIE
0
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Figure 8-2. Timer Control Register (TCR)
= Unimplemented
OCIE
6
0
TOIE
5
0
Figure
U = Undetermined
8-2, performs these functions:
4
0
0
3
0
0
2
0
0
IEDG
U
1
OLVL
Bit 0
Timer I/O Registers
0
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