TN80C31BH1SF88 Intel, TN80C31BH1SF88 Datasheet

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TN80C31BH1SF88

Manufacturer Part Number
TN80C31BH1SF88
Description
IC MPU 8-BIT 5V 16MHZ EXT 44PLCC
Manufacturer
Intel
Series
80Cr
Datasheet

Specifications of TN80C31BH1SF88

Rohs Status
RoHS non-compliant
Core Processor
MCS 51
Core Size
8-Bit
Speed
16MHz
Connectivity
SIO
Peripherals
POR
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
810026

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TN80C31BH1SF88
Manufacturer:
Intel
Quantity:
10 000
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 4 Kbytes of the program memory can reside on-chip (except 80C31BH). In
addition the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 128 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 87C51/80C51BH/80C31BH is a single-chip control-oriented microcontroller which is fabricated on
Intel's reliable CHMOS III-E technology. Being a member of the MCS
87C51/80C51BH/80C31BH uses the same powerful instruction set, has the same architecture, and is pin-for-
pin compatible with the existing MCS 51 controller family of products.
The 80C51BHP is identical to the 80C51BH. When ordering the 80C51BHP, customers must submit the 64
byte encryption table together with the ROM code. Lock bit 1 will be set to enable the internal ROM code
protection and at the same time allows code verification.
The extremely low operating power, along with the two reduced power modes, Idle and Power Down, make
this part very suitable for low power applications. The Idle mode freezes the CPU while allowing the RAM,
timer/counters, serial port and interrupt system to continue functioning. The Power Down mode saves the
RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
For the remainder of this document, the 87C51, 80C51BH, and 80C31BH will be referred to as the 87C51/BH,
unless information applies to a specific device.
High Performance CHMOS EPROM
24 MHz Operation
Improved Quick-Pulse Programming
Algorithm
3-Level Program Memory Lock
Boolean Processor
128-Byte Data RAM
32 Programmable I/O Lines
Two 16-Bit Timer/Counters
Extended Temperature Range
(
* Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT
-
40
°
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
C to
©
+
INTEL CORPORATION, 2004
85
°
C)
87C51/80C51BH/80C31BH
87C51/80C51BH/80C51BHP/80C31BH
*See Table 1 for Proliferation Options
Commercial/Express
July 2004
5 Interrupt Sources
Programmable Serial Port
TTL- and CMOS-Compatible Logic
Levels
64K External Program Memory Space
64K External Data Memory Space
ONCE Mode Facilitates System Testing
Power Control Modes
• Idle
• Power Down
®
51 controller family, the
Order Number: 272335-004

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TN80C31BH1SF88 Summary of contents

Page 1

... Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. ...

Page 2

Standard 80C31BH 80C51BH 80C51BHP 87C51 NOTES: 3.5 MHz to 12 MHz 20 3.5 MHz to 16 MHz 20 0.5 MHz to 12 MHz 20% CC ...

Page 3

... PROCESS INFORMATION The 87C51 manufactured on the CHMOS III-E process. Additional process and reliability informa- tion is available in the Intel ® Quality System Handbook . DIP *Do not connect reserved pins. 87C51/80C51BH/80C31BH PACKAGES Part 87C51-BH 272335– 2 QFP Figure 2. Pin Connections Package Type 40-Pin Plastic ...

Page 4

PIN DESCRIPTION V : Supply voltage during normal, Idle and Power CC Down operations Circuit ground. SS Port 0: Port 8-bit open drain bidirectional I/O port output port each pin can sink ...

Page 5

In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. ...

Page 6

IDLE MODE In Idle Mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the Special Functions Registers remain unchanged during ...

Page 7

... CPU can be used to drive the circuit. Nor- mal operation is restored when a normal reset is ap- plied. 87C51/BH EXPRESS The Intel EXPRESS system offers enhancements to the operational specifications of the MCS-51 family of microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose operating requirements exceed commercial temperature ...

Page 8

ABSOLUTE MAXIMUM RATINGS: Ambient Temperature Under Bias.... Storage Temperature..................... 65 - Voltage on EA/V Pin to V .............. Voltage on Any Other Pin to V ........ SS Maximum I per I/O Pin...................................15 ...

Page 9

Operating Conditions) (Continued) DC CHARACTERISTICS Symbol Parameter (6) V Output Low Voltage OL1 (Port 0, ALE, PSEN) V Output High Voltage OH (Ports ALE, PSEN) V Output High Voltage OH1 (Port 0 in External Bus Mode) ...

Page 10

NOTES: 1. ``Typicals'' are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The values listed are at room temp, 5V. 2. Capacitive loading on Ports 0 and 2 may cause noise ...

Page 11

Figure 6. I Test Condition, Active Mode. All other pins are disconnected. CC 272335 ±8 Figure 7. I Test Condition, Idle Mode. CC All other pins are disconnected. Figure 8. Clock Signal Waveform for I TCLCH 87C51/80C51BH/80C31BH 272335 ±10 Figure ...

Page 12

EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters. The first char- acter is always a `T' (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical ...

Page 13

EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to 87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2. (Continued) Symbol Parameter TPXIX Input Instr Hold After PSEN TPXIZ Input Instr Float After PSEN 87C51/BH 87C51-24/BH-24 ...

Page 14

EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to 87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2. (Continued) Symbol Parameter TWHQX Data Hold After WR 87C51/BH 87C51-24/BH-24 TQVWH Data Valid to WR High ...

Page 15

EXTERNAL DATA MEMORY WRITE CYCLE EXTERNAL CLOCK DRIVE All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to 87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2. Symbol Parameter 1/TCLCL Oscillator Frequency 87C51/BH 87C51-1/BH-1 87C51-2/BH-2 87C51-24/BH-24 TCHCX High Time ...

Page 16

SERIAL PORT TIMING-SHIFT REGISTER MODE 12 MHz Symbol Parameter Oscillator Min TXLXL Serial Port Clock 1.0 Cycle Time TQVXH Output Data Setup 700 to Clock Rising Edge TXHQX Output Data Hold After Clock Rising Edge 87C51/BH 50 87C51-24/BH-24 TXHDX ...

Page 17

PROGRAMMING THE 87C51 The part must be running with a 4 MHz to 6 MHz oscillator. The address of an EPROM location to be programmed is applied to address lines while the code byte to be programmed in that location ...

Page 18

For compatibility, 25 pulses may be used. Figure 11. Programming Waveforms PROGRAMMING ALGORITHM Refer to Table 4 and Figures 10 and 11 for address, data, and control signals set up. To program the 87C51 the following sequence must be ...

Page 19

Program Lock Bits The 87C51 has 3 programmable lock bits that when programmed according to Table 5 will provide differ- ent levels of protection for the on-chip code and data. Erasing the EPROM also erases the encryption ar- ray and ...

Page 20

EPROM PROGRAMMING, EPROM AND ROM VERIFICATION CHARACTERISTICS 10 Symbol Parameter V Programming Supply Voltage PP I Programming Supply Current PP 1/TCLCL Oscillator Frequency TAVGL Address ...

Page 21

... Thermal Impedance All thermal impedance data is approximate for static air conditions power dissipation. Values will change depending on operating conditions and ap- plications. See the Intel Packaging Handbook (Order No. 240800) for a description of Intel's thermal im- pedance test methodology. Device θ θ 87C51 ° ° ...

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