DSP56F805FV80 Freescale Semiconductor, DSP56F805FV80 Datasheet - Page 11

• Manufacturer Part Number: DSP56F805FV80
• Description: IC DSP 80MHZ 31.5K FLASH 144LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxr

Specifications of DSP56F805FV80

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 71KB (35.5K x 16)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.3 Clock and Phase Locked Loop Signals
2.4 Address, Data, and Bus Control Signals
Freescale Semiconductor
No. of
No. of
Pins
Pins
6
2
8
1
1
1
GPIOE2
GPIOA0
EXTAL
GPIOE3
A8–A15
GPIOA7
Signal
CLKO
Name
XTAL
A0–A5
A6–A7
Signal
Name
–
–
Input/O
Signal
Output
Type
Input
utput
Input/O
Input/O
Signal
Output
Output
Output
Type
utput
utput
State During
Chip-driven
Chip-driven
Table 2-6 Address Bus Signals
State During
Reset
Input
Tri-stated
Tri-stated
Tri-stated
Reset
Table 2-5 PLL and Clock
Input
Input
56F805 Technical Data, Rev. 16
External Crystal Oscillator Input—This input should be
connected to an 8MHz external crystal or ceramic resonator. For
more information, please refer to
Crystal Oscillator Output—This output should be connected to
an 8MHz external crystal or ceramic resonator. For more
information, please refer to
This pin can also be connected to an external clock source. For
more information, please refer to
Clock Output—This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select
Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the
device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
Address Bus—A0–A5 specify the address for external
Program or Data memory accesses.
Address Bus—A6–A7 specify the address for external
Program or Data memory accesses.
Port E GPIO—These two General Purpose I/O (GPIO) pins
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
Address Bus—A8–A15 specify the address for external
Program or Data memory accesses.
Port A GPIO—These eight General Purpose I/O (GPIO) pins
can be individually be programmed as input or output pins.
After reset, the default state is Address Bus.
Signal Description
Signal Description
Section
Section
Section
Clock and Phase Locked Loop Signals
3.5.
3.5.
3.5.3.
11