MC68HRC908JK3CP Freescale Semiconductor, MC68HRC908JK3CP Datasheet - Page 92

• Manufacturer Part Number: MC68HRC908JK3CP
• Description: IC MCU FLASH 8B 8MHZ RC 4K 20DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HRC908JK3CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Connectivity: -

System Integration Module (SIM)
7.7.2 Stop Mode
Technical Data
90
NOTE:
NOTE:
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (OSCOUT and 2OSCOUT) in
stop mode, stopping the CPU and peripherals. Stop recovery time is
selectable using the SSREC bit in the configuration register (CONFIG).
If SSREC is set, stop recovery is reduced from the normal delay of 4096
2OSCOUT cycles down to 32. This is ideal for applications using canned
oscillators that do not require long start-up times from stop mode.
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the break status register (BSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period.
To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
R/W
IAB
IDB
instruction.
System Integration Module (SIM)
STOP ADDR
Figure 7-18. Stop Mode Entry Timing
Figure 7-18
PREVIOUS DATA
STOP ADDR + 1
shows stop mode entry timing.
NEXT OPCODE
SAME
MC68H(R)C908JL3
Freescale Semiconductor
SAME
SAME
SAME
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Rev. 1.1