MC908AZ60AMFU Freescale Semiconductor, MC908AZ60AMFU Datasheet - Page 361

• Manufacturer Part Number: MC908AZ60AMFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AMFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

27.6.4 BDLC State Vector Register
This register is provided to substantially decrease the CPU overhead associated with servicing interrupts
while under operation of a multiplex protocol. It provides an index offset that is directly related to the
BDLC’s current state, which can be used with a user-supplied jump table to rapidly enter an interrupt
service routine. This eliminates the need for the user to maintain a duplicate state machine in software.
I0, I1, I2, and I3 — Interrupt Source Bits
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR except when the BDLC data register needs
servicing (RDRF, RXIFR, or TDRE conditions). RXIFR and RDRF can be cleared only by a read of the
BSVR followed by a read of the BDLC data register (BDR). TDRE can either be cleared by a read of the
BSVR followed by a write to the BDLC BDR or by setting the TEOD bit in BCR2.
Freescale Semiconductor
These bits indicate the source of the interrupt request that currently is pending. The encoding of these
bits are listed in
Address:
BSVR
$0C
$1C
$00
$04
$08
$10
$14
$18
$20
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Table
I3
0
0
0
0
0
0
0
0
1
$003E
Bit 7
R
R
0
0
Figure 27-19. BDLC State Vector Register (BSVR)
27-5.
I2
0
0
0
0
1
1
1
1
0
= Reserved
I1
0
0
1
1
0
0
1
1
0
Table 27-5. BDLC Interrupt Sources
R
6
0
0
I0
0
1
0
1
0
1
0
1
0
Cyclical Redundancy Check (CRC) Error
I3
R
BDLC Tx Data Register Empty (TDRE)
5
0
BDLC Rx Data Register Full (RDRF)
Symbol Invalid or Out of Range
Received IFR Byte (RXIFR)
No Interrupts Pending
Loss of Arbitration
Interrupt Source
I2
R
4
0
Received EOF
Wakeup
I1
R
3
0
I0
R
2
0
R
1
0
0
8 (Highest)
0 (Lowest)
Priority
1
2
3
4
5
6
7
BDLC CPU Interface
Bit 0
R
0
0
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