MC68HC908KX2CP Freescale Semiconductor, MC68HC908KX2CP Datasheet
MC68HC908KX2CP
Specifications of MC68HC908KX2CP
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MC68HC908KX2CP Summary of contents
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MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Data Sheet M68HC08 Microcontrollers MC68HC908KX8 Rev. 2.1 07/2005 freescale.com ...
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...
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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserved. ...
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... Table 15-3. Mode, Edge, and Level Selection — Reworked for clarity 17.11 Memory Characteristics — Updated table with new information July, 2.1 Updated to meet Freescale identity guidelines. 2005 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 4 Description Freescale Semiconductor Page Number(s) 19, 20 82, 252, 255 177 183 192 194 ...
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... Chapter 14 Timebase Module (TBM 151 Chapter 15 Timer Interface Module (TIM 155 Chapter 16 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Chapter 17 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Chapter 18 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 193 Appendix A MC68HC908KX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 Appendix B MC68HC08KX8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor 5 ...
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... List of Chapters MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 6 Freescale Semiconductor ...
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... Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Chapter 1 General Description ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.2 Features 6.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 8 Chapter 4 Configuration Register (CONFIG) Chapter 5 Chapter 6 Central Processor Unit (CPU) Freescale Semiconductor ...
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... Ring Oscillator Fine-Adjust Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.5 Switching Internal Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.6 Nominal Frequency Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.6.1 Settling To Within 15 7.4.6.2 Total Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4.7 Trimming Frequency on the Internal Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Chapter 7 9 ...
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... Forced Reset Operation 102 10.3.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.3.4 LVI Trip Selection 102 10.4 LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 10 Chapter 8 External Interrupt (IRQ) Chapter 9 Keyboard Interrupt Module (KBI) Chapter 10 Low-Voltage Inhibit (LVI) Freescale Semiconductor ...
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... Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.6 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.6.1 TxD (Transmit Data 124 12.6.2 RxD (Receive Data 124 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Chapter 11 Input/Output (I/O) Ports (PORTS) Chapter 12 11 ...
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... SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.7.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 13.7.2.1 Interrupt Status Register 149 13.7.2.2 Interrupt Status Register 150 13.7.2.3 Interrupt Status Register 150 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 12 Chapter 13 System Integration Module (SIM) Freescale Semiconductor ...
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... Break Module (BRK 169 16.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.2.1.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Chapter 14 Timebase Module (TBM) Chapter 15 Timer Interface Module (TIM) Chapter 16 Development Support 13 ...
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... Trimmed Internal Clock Generator Characteristics . . . . . . . . . . . . . . . 188 17.9.2 4.5-Volt to 5.5-Volt Trimmed Internal Clock Generator Characteristics . . . . . . . . . . . . . . . 188 17.10 Analog-to-Digital Converter (ADC) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 17.11 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 14 Chapter 17 Electrical Specifications Freescale Semiconductor ...
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... Trimmed Internal Clock Generator Characteristics . . . . . . . . . . . . . 206 B.4.8.2 4.5-Volt to 5.5-Volt Trimmed Internal Clock Generator Characteristics . . . . . . . . . . . . . 206 B.4.9 Analog-to-Digital Converter (ADC) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 B.4.10 Memory Characteristics 207 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Chapter 18 Appendix A MC68HC908KX2 Appendix B MC68HC08KX8 15 ...
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... Table of Contents MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 16 Freescale Semiconductor ...
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... V pin security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor (1) ) double REFH 17 ...
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... Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Third party C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908KX8. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 18 Freescale Semiconductor ...
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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 78 BYTES USER FLASH — 7680 BYTES USER RAM — 192 BYTES MONITOR ROM — 295 BYTES USER FLASH VECTOR SPACE — 36 BYTES FLASH BURN-IN ROM — 1024 ...
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... PTA2/KBD2/TCH0 4 13 IRQ1 PTB4/RxD 5 12 PTB0/AD0 PTB5/TxD 6 11 PTB1/AD1 PTB6/(OSC1 PTB2/AD2 PTB7/(OSC2)/RST 8 9 PTB3/AD3 ) are optional bulk current bypass capacitors for use in Bypass Bulk MCU Bypass 0.1 µ Bulk V DD Figure 1-3. Power Supply Bypassing V SS Freescale Semiconductor ...
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... PTB5 and PTB4 share with the SCI module. See Module (SCI). • PTB3–PTB0 share with the ADC module. See MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Chapter 11 Input/Output (I/O) Ports NOTE ). Although the I/O ports of the MC68HC908KX8 do not SS ) REFH pin ...
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... General Description MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 22 Freescale Semiconductor ...
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... A summary of the available registers is provided in 2.3 Monitor ROM The 295 bytes at addresses $FE20–$FF46 are reserved ROM addresses that contain the instructions for the monitor functions. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor 2-1, includes: Figure 2-2. Table 2 list of vector locations ...
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... FLASH BLOCK PROTECT REGISTER (FLBPR) $FF7F ↓ $FFDB $FFDC ↓ $FFFF Figure 2-1. Memory Map RESERVED RESERVED RESERVED RESERVED LVI STATUS REGISTER (LVISR) UNIMPLEMENTED (18 BYTES) MONITOR ROM (295 BYTES) UNIMPLEMENTED (57 BYTES) UNIMPLEMENTED (90 BYTES) FLASH VECTORS (36 BYTES) Freescale Semiconductor ...
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... Write: See page 129. Reset: Read: SCI Status Register 1 $0016 (SCS1) Write: See page 130. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Bit PTA4 Unaffected by reset PTB7 PTB6 ...
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... Bit Unimplemented Bit BKF RPF SCR2 SCR1 SCR0 KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 TBIE TBON R TACK IRQF1 0 IMASK1 MODE1 R ACK1 EXT- OSCENIN- SCIBDSRC CLKEN STOP LVI5OR3 SSREC STOP COPD PS2 PS1 PS0 Bit Reserved U = Unaffected Freescale Semiconductor ...
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... ICG Control Register for method of clearing the CMF bit. Read: ICG Multiplier Register $0037 (ICGMR) Write: See page 88. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Bit Bit ...
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... POR 0 COP ILOP BCFE IF6 IF5 IF4 IF3 Unimplemented Bit 0 TRIM3 TRIM2 TRIM1 TRIM0 DDIV3 DDIV2 DDIV1 DDIV0 DSTG3 DSTG2 DSTG1 DSTG0 ADCH3 ADCH2 ADCH1 ADCH0 AD3 AD2 AD1 AD0 NOTE ILAD MENRST LVI BDCOP IF2 IF1 Reserved U = Unaffected Freescale Semiconductor ...
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... Write: See page 36. Reset: 1. Non-volatile FLASH register Read: COP Control Register $FFFF (COPCTL) Write: See page 53. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Bit IF14 IF13 IF12 IF11 ...
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... TIM channel 1 vector (high) TIM channel 1 vector (low) TIM channel 0 vector (high) TIM channel 0 vector (low) CMIREQ vector (high) CMIREQ vector (low) IRQ1 vector (high) IRQ1 vector (low) SWI vector (high) SWI vector (low) Reset vector (high) Reset vector (low) Freescale Semiconductor ...
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... Unimplemented Figure 2-3. FLASH Control Register (FLCR security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor NOTE NOTE NOTE NOTE Register. ...
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... Any application can use this 4 ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 32 NOTE Freescale Semiconductor ...
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... When in monitor mode, with security sequence failed (see stead of any FLASH address. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor (1) within the FLASH memory address range. NOTE NOTE 16 ...
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... The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time, t MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 34 (Figure 2 flowchart representation). NOTE (1) . NOTE maximum. See 17.11 PROG maximum. PROG Freescale Semiconductor ...
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... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-4. FLASH Programming Flowchart MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS ...
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... With this mechanism, the protect start address can be $XX00, $XX40, etc., (64 bytes page boundaries) within the FLASH memory. See MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 36 NOTE TST BPR6 BPR5 BPR4 BPR3 Figure 2-6 and Table 2-2. , present on the IRQ pin. This voltage 2 1 Bit 0 BPR2 BPR1 BPR0 Freescale Semiconductor ...
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... Standby mode is the power-saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH minimum. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor 16-BIT MEMORY ADDRESS 0 1 FLBPR VALUE ...
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... Memory MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 38 Freescale Semiconductor ...
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... DDR will not have any effect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a logic 0 if the corresponding DDR bit the DDR bit the value in the port data latch is read. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor as the high voltage reference. PTB0. An analog multiplexer – ...
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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 78 BYTES USER FLASH — 7680 BYTES USER RAM — 192 BYTES MONITOR ROM — 295 BYTES USER FLASH VECTOR SPACE — 36 BYTES FLASH BURN-IN ROM — 1024 ...
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... CGMXCLK frequency of 8 MHz, bus frequency of 2 MHz, and fixed ADC clock frequency of 1 MHz, one conversion will take between 16 and 17 µs and there will be 32 bus cycles between each conversion. Sample rate is approximately 60 kHz. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor DDRBx RESET PTBx ...
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... ADC conversion after exiting stop mode. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 42 Generator ADC clock cycles Conversion time = ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯ ADC clock frequency NOTE 17.9 Trimmed Accuracy of the Freescale Semiconductor ...
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... CPU interrupts enabled (AIEN = 1) Because the MC68HC908KX8 does not have a DMA module, the COCO bit should not be set while interrupts are enabled (AIEN = 1). MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor as its power pin and V as its ground pin. DD ...
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... MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 44 and V REFH NOTE Table 3-1. Mux Channel Select ADCH2 ADCH1 ADCH0 — — — Input selection is detailed in SS Input Select PTB0 PTB1 PTB2 PTB3 (1) Unused — (1) Unused (2) V REFH (2) V SSAD ADC power off Freescale Semiconductor ...
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... ADICLK selects either bus clock or the oscillator output clock (CGMXCLK) as the input clock source to generate the internal ADC rate clock. Reset selects CGMXCLK as the ADC clock source Internal bus clock 0 = Oscillator output clock (CGMXCLK) MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
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... During the conversion process, changing the ADC clock will result in an incorrect conversion. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2 bus frequency CGMXCLK = ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯ ≅ 1 MHz f ADIC ADIV[2:0] NOTE 17.9 Trimmed Accuracy Freescale Semiconductor ...
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... Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 4-2. Address: $001E Bit 7 Read: R Write: Reset Unimplemented Figure 4-1. Configuration Register 2 (CONFIG2) MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor 18 –2 NOTE EXT- EXT- EXT- XTALEN SLOW CLKEN ...
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... OSC1 External oscillator configured for an external crystal configuration on OSC1 and OSC2. System will also OSC2 operate with square-wave clock source in OSC1. Chapter 7 Internal Clock Generator Module NOTE Bit 0 (1) SSREC STOP COPD Chapter 7 Internal Clock Description Freescale Semiconductor ...
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... LVIRSTD disables the reset signal from the LVI module. See 1 = LVI module resets disabled 0 = LVI module resets enabled MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Table 4-1 for configuration options for the external source. See for a more detailed description of the external clock (TBM) ...
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... COPD — COP Disable Bit COPD disables the COP module. See 1 = COP module disabled 0 = COP module enabled MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 50 Chapter 10 Low-Voltage Inhibit NOTE NOTE Chapter 5 Computer Operating Properly Module (LVI). Chapter 10 Low-Voltage . See Chapter 17 DD (COP). Freescale Semiconductor ...
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... COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1) MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor SIM MODULE 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER Figure 5-1 ...
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... The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up. 5.4.5 Internal Reset An internal reset clears the COP prescaler and the COP counter. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2 – NOTE . TST NOTE Figure 5- –2 CGMXCLK Freescale Semiconductor ...
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... The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 5.8.1 Wait Mode The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor (CONFIG). (CONFIG ...
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... To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction. When the STOP bit in the configuration has the STOP instruction disabled, execution of a STOP instruction results in an illegal opcode reset. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 54 Freescale Semiconductor ...
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... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 6.3 CPU Registers Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor 55 ...
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... STACK POINTER (SP) 0 PROGRAM COUNTER (PC CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 6-1. CPU Registers Unaffected by reset Figure 6-2. Accumulator ( Figure 6-3. Index Register (H: Bit 0 Bit Freescale Semiconductor ...
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... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
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... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2 NOTE 2 1 Bit Freescale Semiconductor ...
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... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Arithmetic/Logic Unit (ALU) 59 ...
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... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 – – IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 – – IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...
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... CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Description ← (PC rel ? ( – – – – – – REL PC ← (PC rel ? IRQ = 1 – – – – – – REL PC ← ...
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... DIR INH 4A 1 INH 5A 1 – – – IX1 SP1 9E6A ff 5 INH 52 7 IMM DIR EXT IX2 – IX1 SP1 9EE8 ff 4 SP2 9ED8 DIR INH 4C 1 INH 5C 1 – – – IX1 SP1 9E6C ff 5 Freescale Semiconductor ...
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... ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Effect on CCR Description ← Jump Address – – – – – – PC ← (PC Push (PCL); SP ← (SP) – 1 – ...
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... IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF IMM DIR EXT IX2 IX1 SP1 9EE0 ff 4 SP2 9ED0 Freescale Semiconductor ...
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... Memory location N Negative bit 6.8 Opcode Map See Table 6-2. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Description ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) – – 1 – – – INH SP ← ...
Page 66
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
Page 67
... Functional Description As shown in Figure 7-1, the ICG contains these major submodules: • Clock enable circuit • Internal clock generator • External clock generator • Clock monitor circuit • Clock selection circuit MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor 67 ...
Page 68
... ENABLE CIRCUIT EXTERNAL CLOCK GENERATOR PTB6 OSC1 OSC2 PTB6 PTB7 Figure 7-1. ICG Module Block Diagram CGMOUT CGMXCLK TBMCLK IOFF EOFF ECGS ICGS FICGS DDIV[3:0] DSTG[7:0] ICLK IBASE ICGEN ECGEN ECLK PTB7 LOGIC NAME REGISTER BIT NAME MODULE SIGNAL Freescale Semiconductor ...
Page 69
... The ICG contains: • A digitally controlled oscillator • A modulo "N" divider • A frequency comparator, which contains voltage and current references, a frequency to voltage converter, and comparators • A digital loop filter MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Functional Description 69 ...
Page 70
... TRIM[7:0] FREQUENCY COMPARATOR CLOCK GEN CONFIG (OR MOR) REGISTER BIT TOP LEVEL SIGNAL FICGS DSTG[7:0] DDIV[3:0] DIGITALLY CONTROLLED ICLK OSCILLATOR N[6:0] MODULO "N" DIVIDER IBASE NAME REGISTER BIT NAME MODULE SIGNAL 7.4.4 Quantization Error in DCO ) of 307.2 kHz ± 25%. NOM Freescale Semiconductor ...
Page 71
... When EXTSLOW is clear, the amplifier gain will be sufficient for 1 MHz to 8 MHz crystals. EXTSLOW must be configured correctly for the given crystal or the circuit may not operate. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Table 7-1. In some extreme error conditions, such as Current to New ...
Page 72
... Clock Enable Circuit), and indicates that the external clock function ECLK INPUT PATH AMPLIFIER OSC2 PTB7 * can be 0 (shorted) S when used with higher- frequency crystals. Refer to manufacturer’s data These components are required for external crystal use only. Freescale Semiconductor ...
Page 73
... To simplify the circuit, the low frequency base clock (IBASE) is used in place of ICLK because it always operates at or MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Figure 7-4, contains these blocks: ...
Page 74
... MHz 244 Hz 4096 1*4 (ECLK) 1.953 kHz 16 19.2 kHz 4096*4 (2) ± 25% (IBASE) 4096 75 Hz 16*4 (2) ± 25% (IBASE) Freescale Semiconductor IREF Frequency 0 U 76.8 kHz ± 25% 76.8 kHz ± 25% 76.8 kHz ± 25% 76.8 kHz ± 25% 18.75 Hz ± 125% 4.8 kHz ± 25% ...
Page 75
... CONFIG (or MOR) register is set cycles when EXTXTALEN is clear. ECGS is cleared when the external clock generator is turned off or in STOP (ECGEN is clear) or when EOFF is set. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Figure 7-5, looks for at least one falling edge on the CK ...
Page 76
... EOFF FORCE_I FORCE_E OUTPUT SELECT ICLK ECLK SYNCHRONIZING CLOCK IOFF SWITCHER EOFF FORCE_I FORCE_E CONFIGURATION (OR MOR) REGISTER BIT TOP LEVEL SIGNAL EOFF EGGS NAME REGISTER BIT NAME MODULE SIGNAL CGMXCLK DIV2 CGMOUT TBMCLK NAME REGISTER BIT NAME MODULE SIGNAL Freescale Semiconductor ...
Page 77
... Using clock monitor interrupts • Quantization error in DCO output • Switching internal clock frequencies • Nominal frequency settling time • Improving frequency settling time • Trimming frequency MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Usage Notes 77 ...
Page 78
... These events must happen in sequence. A short assembly code example of how to employ this flow is shown in Figure 7-9. This code is for illustrative purposes only and does not represent valid syntax for any particular assembler. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 78 Freescale Semiconductor ...
Page 79
... The CMISR should take any appropriate precautions. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor ;Clock Monitor Enabling Code Example ;This code turns on both clocks, selects the desired ; one, then turns on the Clock Monitor and Interrupts ...
Page 80
... Freescale Semiconductor ...
Page 81
... Because the clock period of the internal clock (ICLK) is dependent on the digital loop filter outputs (DDIV and DSTG) which cannot change instantaneously, ICLK will temporarily operate at an incorrect clock MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor 7.4.1 Switching Clock 7.4.1 Switching Clock Sources), if desired 7 ...
Page 82
... ICLKFAST ; from half speed to quarter speed ICLKFAST ; and so on. This ICLKFAST /τ , the equation reduces to ICLKFAST τ ) minus get from IBASE IBASE 1 Freescale Semiconductor and τ , not 2 ...
Page 83
... In these applications, reduce power consumption by either selecting a low-frequency external clock and turn the internal clock generator off, or reduce the bus frequency by minimizing the ICG multiplier factor (N) before executing the WAIT instruction. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor τ τ 430 µ ...
Page 84
... When EXTXTALEN is clear, the stabilization divider is configured to 16 cycles since an external clock source does not need a start-up time. The default state for this option is clear. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 84 Freescale Semiconductor ...
Page 85
... See page 88. Reset: Read: ICG Trim Register $0038 (ICGTR) Write: See page 89. Reset: Figure 7-10. ICG Module I/O Register Summary MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Figure 7-10. These registers are: Bit CMF CMIE CMON CS (1) ...
Page 86
... Freescale Semiconductor Bit 0 DDIV0 U DSTG0 R U — — — — — uw — uw — — — ...
Page 87
... ICGON is clear. This bit is forced clear when the clock monitor determines that the external clock (ECLK) is inactive, when ECGON is clear, or during reset External clock (ECLK) sources CGMXCLK 0 = Internal clock (ICLK) sources CGMXCLK MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor CMF ...
Page 88
... N. A value of $00 in this register is interpreted the same as a value of $01. This register cannot be written when the CMON bit is set. Reset sets this factor to $15 (decimal 21) for default frequency of 6.45 MHz ± 25% (1.613 MHz ± 25% bus). MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2 Bit Freescale Semiconductor ...
Page 89
... ICG DCO Stage Register Address: $003A Bit 7 Read: DSTG7 DSTG6 Write: R Reset Unimplemented Figure 7-15. ICG DCO Stage Control Register (ICGDSR) MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor TRIM5 TRIM4 TRIM3 Figure 7-13. ICG Trim Register (ICGTR) ...
Page 90
... ICGON is set to prevent inadvertent frequency shifting. When ICGON is set, DSTG is controlled by the digital loop filter. Since the DCO is active during reset, reset has no effect on DSTG and the value may vary. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 90 Freescale Semiconductor ...
Page 91
... When an interrupt pin is both falling-edge and low-level triggered, the interrupt latch remains set until both of these occur: • Vector fetch or software clear • Return of the interrupt pin to logic 1 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor 91 ...
Page 92
M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 78 BYTES USER FLASH — 7680 BYTES USER RAM — 192 BYTES MONITOR ROM — 295 BYTES USER FLASH VECTOR SPACE — 36 BYTES FLASH BURN-IN ROM — 1024 ...
Page 93
... If the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. • Return of the IRQ1 pin to logic 1 — As long as the IRQ1 pin is at logic 0, the IRQ1 latch remains set. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor DD CLR ...
Page 94
... This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE1 IRQ1 interrupt requests on falling edges and low levels 0 = IRQ1 interrupt requests on falling edges only MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 94 NOTE IRQF1 Reserved U = Unaffected 2 1 Bit 0 0 IMASK1 MODE1 ACK1 Freescale Semiconductor ...
Page 95
... Exit from low-power modes KBD0 . TO PULLUP ENABLE . KB0IE . KBD4 or KBD3 TO PULLUP ENABLE KB4IE or KB3IE Figure 9-1. Keyboard Module Block Diagram MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor ACKK RESET V DD CLR KEYBOARD INTERRUPT FF MODEK INTERNAL BUS VECTOR FETCH DECODER ...
Page 96
M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 78 BYTES USER FLASH — 7680 BYTES USER RAM — 192 BYTES MONITOR ROM — 295 BYTES USER FLASH VECTOR SPACE — 36 BYTES FLASH BURN-IN ROM — 1024 ...
Page 97
... Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Bit ...
Page 98
... Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 98 NOTE Freescale Semiconductor ...
Page 99
... MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
Page 100
... Reset clears the keyboard interrupt enable register PAx pin enabled as keyboard interrupt pin 0 = PAx pin not enabled as keyboard interrupt pin MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 100 KBIE4 KBIE3 Unimplemented 2 1 Bit 0 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...
Page 101
... LVIRSTD, enables the LVI module to generate a reset when Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode. TRIPF MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor voltage falls below the LVI trip falling voltage STOP INSTRUCTION FROM CONFIG ...
Page 102
... HYS NOTE [ V]) may be lower than this. See TRIPF and for the actual trip point voltages configured TRIPF , to be configured for 3-V TRIPF rises above a voltage which TRIPR for the reset recovery greater than TRIPF TRIPR 17.5 Freescale Semiconductor and . by polling ...
Page 103
... LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor voltage was detected below the V DD ...
Page 104
... Low-Voltage Inhibit (LVI) MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 104 Freescale Semiconductor ...
Page 105
... Read: Data Direction Register B $0005 (DDRB) Write: See page 109. Reset: Read: Port A Input Pullup Enable $000D Register (PTAPUE) Write: See page 108. Reset: MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor NOTE Bit PTB7 PTB6 PTB5 DDRA4 ...
Page 106
... Unaffected by reset KBD4 VREFH = Unimplemented Figure 11-2. Port A Data Register (PTA) Chapter 9 Keyboard Interrupt Module Chapter 9 Keyboard Interrupt Module DDRA4 DDRA3 Unimplemented Bit 0 PTA3 PTA2 PTA1 PTA0 KBD3 KBD2 KBD1 KBD0 TCH1 TCH0 (KBI). (KBI Bit 0 DDRA2 DDRA1 DDRA0 Freescale Semiconductor ...
Page 107
... A pins. Each bit is individually configurable and requires that the data direction register, DDRA, bit be configured as an input. Each pullup is automatically disabled when a port bit’s DDRA is configured for output mode. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor NOTE DDRAx RESET ...
Page 108
... PTAPUE4 PTAPUE3 PTB6 PTB5 PTB4 PTB3 Unaffected by reset OSC1 TxD RxD AD3 Figure 11-6. Port B Data Register (PTB) Chapter 7 Internal Clock Generator Module (ICG) (CONFIG). (SCI Bit 0 PTAPUE2 PTAPUE1 PTAPUE0 Bit 0 PTB2 PTB1 PTB0 AD2 AD1 AD0 Freescale Semiconductor and ...
Page 109
... Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from Figure 11-8 shows the port B I/O logic. READ DDRB ($0005) WRITE DDRB ($0005) WRITE PTB ($0001) READ PTB ($0001) MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor (SCI). (ADC DDRB6 DDRB5 ...
Page 110
... MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 110 Table 11-2 summarizes the operation of the port B pins. Table 11-2. Port B Pin Functions Accesses to DDRB Read/Write DDRB7–DDRB0 DDRB7–DDRB0 Accesses to PTB Read Write (1) Pin PTB7–PTB0 PTB7–PTB0 PTB7–PTB0 Freescale Semiconductor ...
Page 111
... Idle receiver input – Receiver overrun – Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor 111 ...
Page 112
M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 78 BYTES USER FLASH — 7680 BYTES USER RAM — 192 BYTES MONITOR ROM — 295 BYTES USER FLASH VECTOR SPACE — 36 BYTES FLASH BURN-IN ROM — 1024 ...
Page 113
... BIT BIT 0 BIT 1 START BIT BIT 0 BIT 1 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Table 12-1 shows the full names and the generic names of the Table 12-1. Pin Name Conventions Generic Pin RxD Names PTB4/RxD 8-BIT DATA FORMAT ...
Page 114
... BKF ENSCI RPF PRE- BAUD RATE SCALER GENERATOR DATA SELECTION ÷ 16 CONTROL Figure 12-3. SCI Module Block Diagram SCI DATA REGISTER TRANSMIT TxD SHIFT REGISTER TXINV R8 T8 ORIE NEIE FEIE PEIE LOOPS ENSCI TRANSMIT CONTROL M WAKE ILTY PEN PTY Freescale Semiconductor ...
Page 115
... Enable the transmitter by writing the transmitter enable bit (TE) in SCI control register 2 (SCC2). 3. Clear the SCI transmitter empty bit by first reading SCI status register 1 (SCS1) and then writing to the SCDR. 4. Repeat step 3 for each subsequent transmission. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Bit LOOPS ENSCI ...
Page 116
... After software clears the SBK bit, the shift register finishes transmitting the last MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 116 INTERNAL BUS ÷ 16 SCI DATA REGISTER 11-BIT TRANSMIT SHIFT REGISTER TXINV M PARITY GENERATION T8 SCTE SCTE SCTIE SCTIE TC TC TCIE TCIE TxD TRANSMITTER CONTROL LOGIC SBK LOOPS ENSCI TE Freescale Semiconductor ...
Page 117
... SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor NOTE 1. Functional Description ...
Page 118
... INTERNAL BUS SCR1 SCR2 SCR0 BAUD ÷ 16 DIVIDER DATA H RECOVERY ALL 0s WAKEUP LOGIC PARITY CHECKING IDLE ILIE SCRF SCRIE OR ORIE NF NEIE FE FEIE PE PEIE SCI DATA REGISTER 11-BIT RECEIVE SHIFT REGISTER RWU SCRF IDLE R8 ILIE SCRIE OR ORIE NF NEIE FE FEIE PE PEIE Freescale Semiconductor ...
Page 119
... When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. RxD SAMPLES RT CLOCK RT CLOCK STATE RT CLOCK RESET MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor START BIT START BIT START BIT DATA QUALIFICATION VERIFICATION SAMPLING Figure 12-7. Receiver Data Sampling Functional Description ...
Page 120
... Table 12-2. Start Bit Verification Start Bit Verification 000 Yes 001 Yes 010 Yes 011 No 100 Yes 101 No 110 No 111 No Table 12-3. Data Bit Recovery Data Bit Determination 000 0 001 0 010 0 011 1 100 0 101 1 110 1 111 1 NOTE Noise Flag Noise Flag Freescale Semiconductor ...
Page 121
... RECEIVER RT CLOCK For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × cycles + 10 RT cycles = 154 RT cycles. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Table 12-4. Stop Bit Recovery Framing Error Flag 000 ...
Page 122
... STOP IDLE OR NEXT CHARACTER DATA SAMPLES Figure 12-9. Fast Data Figure 12-9, the receiver counts 154 RT cycles at the point 154 160 – × 100 = 3.90%. ------------------------- - 154 Figure 12-9, the receiver counts 170 RT cycles at the point Freescale Semiconductor ...
Page 123
... SCDR. The previous character remains in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI error CPU interrupt requests. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor 170 176 – × ...
Page 124
... The RxD pin is the serial data input to the SCI receiver. The SCI shares the RxD pin with port B. When the SCI is enabled, the RxD pin is an input regardless of the state of the DDRB4 bit in data direction register B (DDRB). MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 124 Freescale Semiconductor ...
Page 125
... This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit SCI enabled 0 = SCI disabled MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
Page 126
... Changing the PTY bit in the middle of a transmission or reception can generate a parity error. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 126 NOTE Table 12-5.) When enabled, the parity function Figure 12-2.) Reset clears the PEN bit. NOTE Table 12-5.) Freescale Semiconductor ...
Page 127
... This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears the TCIE bit enabled to generate CPU interrupt requests not enabled to generate CPU interrupt requests MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Table 12-5. Character Format Selection Character Format Start Data ...
Page 128
... Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 128 NOTE NOTE NOTE Freescale Semiconductor ...
Page 129
... This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE. Reset clears FEIE SCI error CPU interrupt requests from FE bit enabled 0 = SCI error CPU interrupt requests from FE bit disabled MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
Page 130
... Reset sets the TC bit transmission in progress 0 = Transmission in progress MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 130 NOTE SCRF IDLE Unimplemented 2 1 Bit Freescale Semiconductor ...
Page 131
... FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit Framing error detected framing error detected MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor I/O Registers 131 ...
Page 132
... READ SCDR BYTE 1 BYTE 2 DELAYED FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1 SCRF = READ SCDR BYTE 1 Figure 12-14. Flag Clearing Sequence Unimplemented BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = READ SCDR BYTE Bit 0 0 BKF RPF Freescale Semiconductor ...
Page 133
... SCI Baud Rate Register The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter. Address: $0019 Bit 7 Read: 0 Write: Reset: 0 Figure 12-17. SCI Baud Rate Register (SCBR) MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
Page 134
... MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 134 Table 12-6. SCI Baud Rate Prescaling Prescaler Divisor (PD Table 12-7. SCI Baud Rate Selection Baud Rate Divisor (BD 128 f BAUDCLK = ----------------------------------- - × × Table 12-6. Reset clears SCP1 Table 12-7. Reset clears Freescale Semiconductor ...
Page 135
... MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Baud Rate SCR[2:1:0] Divisor (f BAUDCLK (BD) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 000 1 001 2 010 4 011 8 100 16 101 32 110 ...
Page 136
... Serial Communications Interface Module (SCI) MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 136 Freescale Semiconductor ...
Page 137
... See page 149. Reset: Read: Interrupt Status Register 2 $FE05 (INT2) Write: See page 150. Reset: Read: Interrupt Status Register 3 $FE06 (INT3) Write: See page 150. Reset: MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Bit POR 0 COP IF6 IF5 IF4 ...
Page 138
... COP CLOCK CGMXCLK (FROM ICG) CGMOUT (FROM ICG) INTERNAL CLOCKS FORCED MON MODE ENTRY (FROM MENRST MODULE) LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE Freescale Semiconductor ...
Page 139
... In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor CGMXCLK A CGMOUT ÷ ...
Page 140
... MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 140 and 13.7.1 SIM Reset Status Register. NOTE Figure 13-5. ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST INTERNAL RESET LVI POR MENRST Figure 13-4. Sources of Internal Reset 64 CYCLES Figure 13-5. Internal Reset Timing VECTOR HIGH Freescale Semiconductor ...
Page 141
... The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor 64 CYCLES Figure 13-6. POR Recovery while the MCU is in monitor mode ...
Page 142
... The SIM counter is free-running after all reset states. See counter control and internal reset recovery sequences. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 142 (LVI). 13.3.1 Active Resets from Internal Sources voltage falls to the V DD TRIPF rises DD for Freescale Semiconductor ...
Page 143
... CPU uses to determine which vector to fetch. As shown in 13-9, once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced or the I bit is cleared. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Figure 13-8 shows interrupt recovery timing. SP – – ...
Page 144
... I BIT SET? NO YES IRQ1 INTERRUPT ? NO YES ICG CLK MON INTERRUPT ? NO OTHER YES INTERRUPTS ? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION ? NO RTI YES UNSTACK CPU REGISTERS INSTRUCTION ? NO EXECUTE INSTRUCTION Figure 13-9. Interrupt Processing SET I BIT Freescale Semiconductor ...
Page 145
... The SIM holds the CPU in a non-clocked state. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. Low-power modes are exited via an interrupt or reset. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor NOTE CLI LDA ...
Page 146
... MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 146 WAIT ADDR + 1 SAME NEXT OPCODE Figure 13-11. Wait Mode Entry Timing show the timing for WAIT recovery. $DE0C $00FF $00FE $A6 $01 $0B $DE 64 CYCLES $A6 Figure 13-11 SAME SAME SAME $00FD $00FC RST VCT H RST VCT L Freescale Semiconductor ...
Page 147
... Note: Previous data can be operand data or the STOP opcode, depending on the last instruction. CGMXCLK INT IAB STOP +1 Figure 13-15. Stop Mode Recovery from Interrupt MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor NOTE Figure 13-14 STOP ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 13-14 ...
Page 148
... Last reset was caused by the MENRST circuit 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset was caused by the LVI circuit 0 = POR or read of SRSR MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 148 COP ILOP ILAD Unimplemented 2 1 Bit 0 MENRST LVI Freescale Semiconductor ...
Page 149
... IF5–IF1 — Interrupt Flags and 1 These flags indicate the presence of interrupt requests from the sources shown Interrupt request present interrupt request present MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Table 13-2. Interrupt Sources INT (1) Flag Register ...
Page 150
... These flags indicate the presence of interrupt requests from the sources shown Interrupt request present interrupt request present MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 150 IF13 IF12 IF11 IF10 Reserved IF21 IF20 IF19 IF18 Reserved 2 1 Bit 0 IF9 IF8 IF7 Table 13- Bit 0 IF17 IF16 IF15 Table 13-2. Freescale Semiconductor ...
Page 151
... TBR2–TBR0. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. Interrupts must be acknowledged by writing the TACK bit. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Figure 14-1, starts 151 ...
Page 152
... Timebase Module (TBM) TBMCLK FROM ICG MODULE ÷ 2 ÷ 2 ÷ 2 ÷ 2 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 152 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 Figure 14-1. Timebase Block Diagram TBON TBMINT TBIF Freescale Semiconductor TBIE ...
Page 153
... In stop mode, the timebase register is not accessible by the CPU. If the timebase functions are not required during stop mode, reduce power consumption by disabling the timebase module before executing the STOP instruction. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor 1 Divider = ...
Page 154
... The counter can be initialized by clearing and then setting this bit. Reset clears the TBON bit Timebase is enabled Timebase is disabled and the counter initialized to 0s. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 154 TBR2 TBR1 TBR0 TACK Unimplemented R NOTE 2 1 Bit 0 TBIE TBON Reserved Freescale Semiconductor ...
Page 155
... The two TIM channels are programmable independently as input capture or output compare channels. Figure 15-3 summarizes the timer registers. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Table 15-1. Pin Name Conventions TCH0 PTA2/KBD2/TCH0 Figure 15-2 ...
Page 156
M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 78 BYTES USER FLASH — 7680 BYTES USER RAM — 192 BYTES MONITOR ROM — 295 BYTES USER FLASH VECTOR SPACE — 36 BYTES FLASH BURN-IN ROM — 1024 ...
Page 157
... Write: See page 164. Reset: Read: Timer Counter Modulo $0023 Register High (TMODH) Write: See page 165. Reset: MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor PRESCALER SELECT PS2 PS1 PS0 ELS0B ELS0A CH0F MS0A MS0B ELS1B ELS1A ...
Page 158
... CH0F CH0IE MS0B MS0A Bit Indeterminate after reset Bit Indeterminate after reset CH1F 0 CH1IE MS1A Bit Indeterminate after reset Bit Indeterminate after reset = Unimplemented Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit Bit 0 ELS1B ELS1A TOV1 CH1MAX Bit Bit 0 Freescale Semiconductor ...
Page 159
... TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor NOTE Functional Description 15 ...
Page 160
... MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 160 15.8.1 TIM Status and Control OVERFLOW PERIOD PULSE WIDTH OUTPUT OUTPUT COMPARE COMPARE NOTE Register. OVERFLOW OUTPUT COMPARE 15.4.6 Pulse-Width Freescale Semiconductor ...
Page 161
... Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor NOTE Table Table 15-2. ...
Page 162
... TCH0 can be configured as buffered output compare or buffered PWM pins. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 162 15.8.4 TIM Channel Status and Control Registers. Freescale Semiconductor ...
Page 163
... TSTOP bit, stopping the TIM counter until software clears the TSTOP bit TIM counter stopped 0 = TIM counter active Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
Page 164
... Internal bus clock ÷1 Internal bus clock ÷ 2 Internal bus clock ÷ 4 Internal bus clock ÷ 8 Internal bus clock ÷ 16 Internal bus clock ÷ 32 Internal bus clock ÷ 64 Not available TCNTH — $0021 TCNTL — $0022 Unimplemented 2 1 Bit Bit Bit Bit Freescale Semiconductor ...
Page 165
... CH0F Write: 0 Reset: 0 Register name and address: Bit 7 Read: CH1F Write: 0 Reset Unimplemented Figure 15-8. TIM Channel Status and Control Registers (TSCO and TSC1) MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor TMODH — $0023 TMODL — $0024 6 ...
Page 166
... When ELSxB and ELSxA are both clear, channel x is not connected to port A, and pin PTAx/TCHx is available as a general-purpose I/O pin. the ELSxB and ELSxA bits. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 166 Table 15-3. NOTE Table 15-3 shows how ELSxB and ELSxA work. Reset clears Table 15-3. Freescale Semiconductor ...
Page 167
... TOVx bit (CHxMAX = 0). The PWM 100 percent duty cycle is defined as output high all of the time. To generate the 100 percent duty cycle, use the CHxMAX bit in the TSCx register. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor ELSxA Mode 0 Pin under port control ...
Page 168
... Figure 15-9. CHxMAX Latency TCH0H — $0026 Indeterminate after reset TCH0L — $0027 Indeterminate after reset TCH1H — $0029 Indeterminate after reset TCH1L — $002A Indeterminate after reset OVERFLOW OVERFLOW OUTPUT COMPARE 2 1 Bit Bit Bit Bit Bit Bit Bit Bit 0 Freescale Semiconductor ...
Page 169
... Flag Protection During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Figure 16-1 shows the 169 ...
Page 170
... MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 170 IAB15–IAB8 BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB7–IAB0 Bit BCFE Bit Bit BRKE BRKA Unimplemented Figure 16-2. I/O Register Summary CONTROL BREAK NOTE Reserved Freescale Semiconductor Bit Bit 8 0 Bit BDCOP 0 ...
Page 171
... This read/write status and control bit is set when a break address match occurs. Writing BRKA generates a break interrupt. Clear BRKA by writing before exiting the break routine. Reset clears the BRKA bit When read, break address match 0 = When read, no break address match MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
Page 172
... No break interrupt during wait mode BW can be read within the break interrupt routine. The user can modify the return address on the stack by subtracting 1 from it. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 172 Reserved 2 1 Bit Bit Bit Bit Bit NOTE Freescale Semiconductor ...
Page 173
... SBSW is set. Clear the BW bit by writing 0 to it. 16.2.3.2 Stop Mode A break interrupt causes exit from stop mode and sets the BW bit in the break status register. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
Page 174
... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 174 ( reset vector is blank ($FFFE and $FFFF contain TST , is applied to IRQ TST Table 16-1 shows the pin Freescale Semiconductor ...
Page 175
... DB- Figure 16-9. Normal Monitor Mode Circuit $FFFE/ IRQ1 PTB1 Pin $FFFF Pin (PTXMOD1 TST $ blank MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor µ µF DD 0.1 µ MC74HC125 Table 16-1. Monitor Mode Entry PTB0 Pin PTA1 ...
Page 176
... TST will revert PTB7/(OSC2)/RST TST , the COP module is controlled by the TST , the MCU will come out of reset in user mode. The TST Reset Vector Low SWI Vector High $FFFF $FFFC $FEFF $FEFC is TST SWI Vector Low $FFFD $FEFD Freescale Semiconductor ...
Page 177
... Table 16-3. Normal Monitor Mode Baud Rate Selection CGMXCLK Frequency (MHz) MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor 16.3.2 BIT 6 BIT 2 BIT 3 ...
Page 178
... MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 178 NOTE ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Figure 16-12. Read Transaction ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Figure 16-13. Write Transaction DATA RETURN DATA DATA Freescale Semiconductor ...
Page 179
... Read next 2 bytes in memory from last address accessed Operand 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode $1A ECHO MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Command Sequence ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW ...
Page 180
... Operand None Data Returned None Opcode $28 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 180 Command Sequence FROM HOST DATA DATA IWRITE IWRITE ECHO Command Sequence SP READSP READSP HIGH Command Sequence FROM HOST RUN RUN ECHO SP LOW RETURN Freescale Semiconductor ...
Page 181
... If the received bytes do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading FLASH locations returns undefined data, and trying to execute code from FLASH causes an illegal address reset. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor SP HIGH BYTE OF INDEX REGISTER ...
Page 182
... The MCU does not transmit a break character until after the host sends the eight security bytes. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 182 24 CGMXCLK CYCLES 256 CGMXCLK CYCLES (ONE BIT TIME NOTE Freescale Semiconductor ...
Page 183
... For proper operation recommended that V ≤ Out inputs are connected to an appropriate logic voltage level (for example, either MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor NOTE Characteristics, and for guaranteed (1) Symbol –I PTA0 I MVSS ...
Page 184
... MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 184 Symbol Symbol θ I and measured Value Unit °C –40 to 125 3.0 ± 10% V 5.0 ± 10% Value Unit °C User determined I/O W K/(T + 273° 273° W/° θ θ ° °C 135 With this value and D. D Freescale Semiconductor ...
Page 185
... OSCSTOPEN option is not selected Pullups and pulldowns are disabled. 8. Maximum is highest voltage that POR is guaranteed. 9. Maximum is highest voltage that POR is possible. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Symbol Min V –0.4 DD ...
Page 186
... V + 4.0 — 2.45 2.60 2.70 2.55 2.66 2.80 — 60 — 24 — 3.3 Vdc. All inputs 0.2 V from rail Freescale Semiconductor Unit µA µA µ V/ kΩ ...
Page 187
... Bus EXTOSC 9. Consult crystal vendor data sheet, see 10. Not required for high-frequency crystals MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Symbol f 230.4 INTOSC f OSC_TOL N = –40°C to +125°C, unless otherwise noted A Symbol ...
Page 188
... V ar_volt — — and temperature, as temperature and V DD Typ Max Unit 2.5 5.0 % 4.0 5.7 0.03 0.05 %/C 0.5 2.0 %/V 0.7 2.0 0.7 2.0 DD Typ Max Unit 4.0 7.0 % 5.0 10.0 0.05 0.08 %/C 1.0 2.0 %/V 1.0 2.0 1.0 2.0 DD Freescale Semiconductor ...
Page 189
... Figure 17-2. Example of Frequency Variation Across Temperature, Trimmed at Nominal 3 Volts, 25°C, and N = 104 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Trimmed Accuracy of the Internal Clock Generator illustrate typical performance. The formula for this variation of frequency Figure 17-1 ...
Page 190
... Figure 17-4. Example of Frequency Variation Across Temperature, Trimmed at Nominal 5 Volts, 25°C, and N = 104 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 190 - 0.002145923 -0.025751073 -0.036480687 0 -0.021459227 -0.034334764 0.006437768 -0.019313305 -0.030042918 , , - -0.001573799 -0.045660099 0 -0.052393569 -0.009064287 -0.047532721 4.5 5 5.5 125 4.5 5 5.5 125 -0.073709584 -0.076379066 -0.077255613 Freescale Semiconductor ...
Page 191
... Power-up time Conversion time Sample time Monotocity Zero input reading Full-scale reading Input capacitance 1. One count is 1/256 shared with REFH DD REFL MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) Characteristics Symbol Min Max V 2.7 5 ADIN – ...
Page 192
... V 1 — — MHz 0 — 0.9 1 1.1 ms 3.6 4 5.5 4 — — ms µs 10 — — µs 5 — — µs 100 — — µs 5 — — µs 30 — 40 µs 1 — — — — 100 k — Cycles 15 100 — Years Freescale Semiconductor ...
Page 193
... MC Order Numbers MC Order Number MC68HC908KX8CP MC68HC908KX8CDW MC68HC908KX8VP MC68HC908KX8VDW MC68HC908KX8MP MC68HC908KX8MDW MC68HC908KX2CP MC68HC908KX2CDW MC68HC908KX2VP MC68HC908KX2VDW MC68HC908KX2MP MC68HC908KX2MDW Plastic dual in-line package DW = Small outline package MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Table 18-1 ...
Page 194
... PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 ° ° θ Freescale Semiconductor ...
Page 195
... A security feature prevents viewing of the FLASH contents. See 2.6 FLASH Control Register 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Figure A-1. NOTE Register. (1) for a complete description of FLASH operation ...
Page 196
... LVI STATUS REGISTER (LVISR) $FE0D ↓ UNIMPLEMENTED (19 BYTES) $FE1F $FE20 ↓ MONITOR ROM (295 BYTES) $FF46 $FF47 ↓ UNIMPLEMENTED (55 BYTES) $FF7D $FF7E FLASH BLOCK PROTECT REGISTER (FLBPR) $FF7F ↓ UNIMPLEMENTED (93 BYTES) $FFDB $FFDC FLASH VECTORS ↓ (36 BYTES) $FFFF Freescale Semiconductor ...
Page 197
... MENRST has no function in the ROM version and reading this bit will return 0. • FLASH test control register, FLTCR • FLASH control register, FLCR • FLASH block protect register, FLBPR MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor Figure B-1. 13.3.1.5 Forced Monitor Mode 13.7.1 SIM Reset Status Register. 197 ...
Page 198
M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 78 BYTES USER ROM — 7680 BYTES USER RAM — 192 BYTES MONITOR ROM — 296 BYTES USER ROM VECTOR SPACE — 36 BYTES INTERNAL CLOCK GENERATOR MODULE SOFTWARE ...
Page 199
... CONFIG can be written once after each reset security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the ROM difficult for unauthorized users. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 Freescale Semiconductor (1) . The memory programming interface, and in 16 ...
Page 200
... Description. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1 200 EXTXTALEN EXTSLOW EXTCLKEN Unaffected by reset LVIRSTD LVIPWRD LVI5OR3 Unaffected by reset NOTE 2 1 Bit 0 0 OSCEINSTOP SCIBDSRC 2 1 Bit 0 SSREC STOP COPD 4.2 Functional Freescale Semiconductor ...