C8051F331 Silicon Laboratories Inc, C8051F331 Datasheet
C8051F331
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C8051F331 Summary of contents
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Analog Peripherals - 10-Bit ADC (‘F330 and ‘F330D only) • 200 ksps • external single-ended or differential inputs • VREF from internal VREF, external pin or V • Internal or external start of conversion source ...
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C8051F330/1, C8051F330D 2 Rev. 1.2 ...
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Table of Contents 1. System Overview.................................................................................................... 13 1.1. CIP-51™ Microcontroller Core.......................................................................... 16 1.1.1. Fully 8051 Compatible.............................................................................. 16 1.1.2. Improved Throughput ............................................................................... 16 1.1.3. Additional Features .................................................................................. 17 1.2. On-Chip Memory............................................................................................... 18 1.3. On-Chip Debug Circuitry................................................................................... 19 1.4. Programmable Digital I/O ...
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C8051F330/1, C8051F330D 9.2.5. Stack ....................................................................................................... 72 9.2.6. Special Function Registers....................................................................... 73 9.2.7. Register Descriptions ............................................................................... 76 9.3. Interrupt Handler ............................................................................................... 79 9.3.1. MCU Interrupt Sources and Vectors ........................................................ 79 9.3.2. External Interrupts .................................................................................... 80 9.3.3. Interrupt Priorities ..................................................................................... 80 9.3.4. ...
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Operation ........................................................................................... 127 15.3.1.Arbitration............................................................................................... 127 15.3.2.Clock Low Extension.............................................................................. 128 15.3.3.SCL Low Timeout................................................................................... 128 15.3.4.SCL High (SMBus Free) Timeout .......................................................... 128 15.4.Using the SMBus............................................................................................ 129 15.4.1.SMBus Configuration Register............................................................... 130 15.4.2.SMB0CN Control Register ..................................................................... 133 15.4.3.Data Register ......................................................................................... 136 15.5.SMBus Transfer ...
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C8051F330/1, C8051F330D 19.1.PCA Counter/Timer ........................................................................................ 188 19.2.Capture/Compare Modules ............................................................................ 189 19.2.1.Edge-triggered Capture Mode................................................................ 190 19.2.2.Software Timer (Compare) Mode........................................................... 192 19.2.3.High-Speed Output Mode ...................................................................... 193 19.2.4.Frequency Output Mode ........................................................................ 194 19.2.5.8-Bit Pulse Width Modulator Mode......................................................... 195 19.2.6.16-Bit Pulse Width Modulator Mode....................................................... ...
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... List of Figures And Tables 1. System Overview Table 1.1. Product Selection Guide ........................................................................ 14 Figure 1.1. C8051F330 and C8051F330D Block Diagram....................................... 15 Figure 1.2. C8051F331 Block Diagram .................................................................... 15 Figure 1.3. Comparison of Peak MCU Execution Speeds ....................................... 16 Figure 1.4. On-Chip Clock and Reset ...................................................................... 17 Figure 1.5. On-Board Memory Map.......................................................................... 18 Figure 1 ...
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C8051F330/1, C8051F330D Figure 5.15. ADC Window Compare Example: Right-Justified Single-Ended Data . 47 Figure 5.16. ADC Window Compare Example: Left-Justified Single-Ended Data.... 47 Figure 5.17. ADC Window Compare Example: Right-Justified Differential Data...... 48 Figure 5.18. ADC Window Compare Example: Left-Justified ...
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Figure 10.3. VDM0CN: VDD Monitor Control ........................................................... 91 Figure 10.4. RSTSRC: Reset Source Register ........................................................ 93 Table 10.1. Reset Electrical Characteristics............................................................. 94 11. Flash Memory Table 11.1. Flash Electrical Characteristics ............................................................. 96 Figure 11.1. Flash Program Memory Map................................................................ 97 Figure ...
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C8051F330/1, C8051F330D Figure 15.5. SMB0CF: SMBus Clock/Configuration Register ................................ 132 Figure 15.6. SMB0CN: SMBus Control Register.................................................... 134 Table 15.3. Sources for Hardware Changes to SMB0CN ...................................... 135 Figure 15.7. SMB0DAT: SMBus Data Register...................................................... 136 Figure 15.8. Typical Master Transmitter Sequence................................................ ...
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Timers Figure 18.1. T0 Mode 0 Block Diagram.................................................................. 172 Figure 18.2. T0 Mode 2 Block Diagram.................................................................. 173 Figure 18.3. T0 Mode 3 Block Diagram.................................................................. 174 Figure 18.4. TCON: Timer Control Register ........................................................... 175 Figure 18.5. TMOD: Timer Mode Register ...
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C8051F330/1, C8051F330D Figure 19.17. PCA0CPHn: PCA Capture Module High Byte.................................. 203 20. C2 Interface Figure 20.1. C2ADD: C2 Address Register ............................................................ 205 Figure 20.2. DEVICEID: C2 Device ID Register..................................................... 205 Figure 20.3. REVID: C2 Revision ID Register ........................................................ 206 Figure ...
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System Overview C8051F330/1, C8051F330D devices are fully integrated mixed-signal System-on-a-Chip MCUs. High- lighted features are listed below. Refer to Table 1.1 for specific product feature selection. • High-speed pipelined 8051-compatible microcontroller core ( MIPS) • In-system, full-speed, ...
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... C8051F330/1, C8051F330D Table 1.1. Product Selection Guide C8051F330 25 8k 768 C8051F330D 25 8k 768 C8051F331 25 8k 768 Rev. 1.2 MLP-20 DIP-20 - MLP-20 ...
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... C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit System Clock 24.5MHz (2%) Internal Oscillator 80 kHz Internal Oscillator Figure 1.2. C8051F331 Block Diagram C8051F330/1, C8051F330D Port 0 Latch UART Timer 3-Chnl PCA/ WDT 8kbyte 8 FLASH SMBus 0 SPI 256 byte 5 SRAM ...
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C8051F330/1, C8051F330D 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F330/1, C8051F330D family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compil- ers can be used ...
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Additional Features The C8051F330/1, C8051F330D SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides 14 interrupt sources into the CIP-51 (as ...
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C8051F330/1, C8051F330D 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, ...
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On-Chip Debug Circuitry The C8051F330/1, C8051F330D devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that pro- vides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application. Silicon Labs' debugging system supports inspection and ...
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C8051F330/1, C8051F330D 1.4. Programmable Digital I/O and Crossbar C8051F330/1, C8051F330D devices include 17 I/O pins (two byte-wide Ports and one 1-bit-wide Port). The C8051F330/1, C8051F330D Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be ...
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Serial Ports The C8051F330/1, C8051F330D Family includes an SMBus/I enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully imple- mented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring ...
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C8051F330/1, C8051F330D 1.7. 10-Bit Analog to Digital Converter The C8051F330 and C8051F330D devices include an on-chip 10-bit SAR ADC with a 16-channel differen- tial input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with ...
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Comparators C8051F330/1, C8051F330D devices include an on-chip voltage comparator that is enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port ...
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C8051F330/1, C8051F330D 1.9. 10-bit Current Output DAC The C8051F330 and C8051F330D device includes a 10-bit current-mode Digital-to-Analog Converter (IDA0). The maximum current output of the IDA0 can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 ...
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Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or /RST with respect to GND V Voltage on DD with respect to GND V Maximum Total current ...
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C8051F330/1, C8051F330D 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Voltage V Digital Supply Current with DD = 2.7 V, Clock = 25 ...
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Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F330/1, C8051F330D Pin Pin Name ‘F330/1 ‘F330D GND 2 5 /RST C2CK P2. C2D P0. VREF P0 ...
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C8051F330/1, C8051F330D Table 4.1. Pin Definitions for the C8051F330/1, C8051F330D (Continued) Pin Pin Name ‘F330/1 ‘F330D P0. CNVSTR P1.5 8 ...
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GND P0.0 1 GND 2 VDD 3 /RST/C2CK 4 P2.0/C2D 5 Figure 4.1. MLP-20 Pinout Diagram (Top View) C8051F330/1, C8051F330D C8051F330/1 Top View GND Rev. 1.2 15 P0.6 14 P0.7 13 P1.0 12 P1.1 11 P1.2 29 ...
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C8051F330/1, C8051F330D Bottom View DETAIL Side View DETAIL Figure 4.2. MLP-20 Package Drawing Rev. 1.2 Table ...
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L 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 4.3. Typical MLP-20 Solder Paste Mask C8051F330/1, C8051F330D Top View 0.60 mm 0.60 mm 0.30 mm 0.20 mm 0.40 mm ...
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C8051F330/1, C8051F330D 0.50 mm 0.20 mm Optional GND Connection 0. 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 4.4. Typical MLP-20 Landing Diagram 32 Top View E2 E Rev. 1.2 0.85 mm ...
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C8051F330/1, C8051F330D ...
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C8051F330/1, C8051F330D 20 Top View PIN 1 IDENTIFIER 1 Side View Pin Dimensions (Bottom View) b1 Base c c1 Metal b Figure 4.6. DIP-20 Package Drawing 34 Table 4.3. DIP-20 Package Dimensions A E1 ...
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ADC (ADC0, C8051F330 and C8051F330D only) The ADC0 subsystem for the C8051F330 and C8051F330D consists of two analog multiplexers (referred to collectively as AMUX0) with 16 total input selections, and a 200 ksps, 10-bit successive-approximation- register ADC with ...
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C8051F330/1, C8051F330D 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive input: Ports0-1, the on-chip temperature sensor, or the positive power supply ( following may be ...
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Temperature Sensor The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (V positive ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. (Volts) 1.000 0.900 0.800 0.700 0.600 0.500 ...
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C8051F330/1, C8051F330D 5.3. Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by ...
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Tracking Modes Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to be accurate. The minimum tracking time is given in Table 5.1. The AD0TM bit in register ADC0CN controls the ...
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C8051F330/1, C8051F330D 5.3.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the ...
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Bit7 Bit6 Bit5 Bits7-5: UNUSED. Read = 000b; Write = don’t care. Bits4-0: AMX0P4-0: AMUX0 Positive Input Selection AMX0P4-0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 ...
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C8051F330/1, C8051F330D Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0N4–0: AMUX0 Negative Input Selection. Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended ...
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R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4-0. ...
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C8051F330/1, C8051F330D R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data ...
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Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space ...
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C8051F330/1, C8051F330D R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: High byte of ADC0 Less-Than Data Word Figure 5.13. ADC0LTH: ADC0 Less-Than Data High Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Low byte of ADC0 Less-Than Data Word Figure ...
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Window Detector In Single-Ended Mode Figure 5.15 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF x ...
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C8051F330/1, C8051F330D 5.4.2. Window Detector In Differential Mode Figure 5.17 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is ...
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Table 5.1. ADC0 Electrical Characteristics VDD = 3.0 V, VREF = 2.40 V (REFSL=0), -40 to +85 °C unless otherwise specified. Parameter Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic performance (10 kHz sine-wave ...
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C8051F330/1, C8051F330D 50 Rev. 1.2 ...
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Current Mode DAC (IDA0, C8051F330 and C8051F330D only) The C8051F330 and C8051F330D device includes a 10-bit current-mode Digital-to-Analog Converter (IDAC). The maximum current output of the IDAC can be adjusted for three different current settings; 0.5 mA, 1 ...
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C8051F330/1, C8051F330D 6.1.2. Update Output Based on Timer Overflow Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow indepen- dently of the processor, the IDAC outputs can use a Timer overflow to ...
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R/W R/W R/W IDA0EN IDA0CM Bit7 Bit6 Bit5 Bit 7: IDA0EN: IDA0 Enable. 0: IDA0 Disabled. 1: IDA0 Enabled. Bits 6-4: IDA0CM[2:0]: IDA0 Update Source Select bits. 000: DAC output updates on Timer 0 overflow. 001: DAC output updates on ...
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C8051F330/1, C8051F330D R/W R Bit7 Bit6 Bit5 Bits 7-6: IDA0 Data Word Low-Order Bits. Lower 2 bits of the 10-bit Data Word. Bits 5-0: UNUSED. Read = 000000b, Write = don’t care. Figure 6.5. IDA0L: IDA0 Data Word ...
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Voltage Reference (C8051F330 and C8051F330D only) The Voltage reference MUX on C8051F330/1, C8051F330D devices is configurable to use an externally connected voltage reference, the internal reference voltage generator, or the (see Figure 7.1). The REFSL bit in the Reference ...
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C8051F330/1, C8051F330D Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF pin used as ...
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Table 7.1. Voltage Reference Electrical Characteristics VDD = 3.0 V; –40 to +85 °C unless otherwise specified. Parameter Output Voltage VREF Short-Circuit Current VREF Temperature Coefficient Load Regulation Load = 0 to 200 µA to AGND VREF Turn-on Time 1 ...
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C8051F330/1, C8051F330D 58 Rev. 1.2 ...
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Comparator0 C8051F330/1, C8051F330D devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 8.1. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a ...
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C8051F330/1, C8051F330D The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system clock; the ...
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Comparator falling-edge occurrence, and the CP0RIF flag is set to logic 1 upon the Com- parator rising-edge occurrence. Once set, these bits remain set until cleared by software. The Comparator rising-edge interrupt mask is enabled ...
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C8051F330/1, C8051F330D R/W R/W R/W CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3 CMX0P2 CMX0P1 CMX0P0 Bit7 Bit6 Bit5 Bits7-4: CMX0N2-CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 negative input. CMX0N3 CMX0N2 CMX0N1 CMX0N0 ...
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CP0RIE Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 Rising-edge interrupt disabled. 1: Comparator0 Rising-edge interrupt enabled. Bit4: CP0FIE: Comparator0 Falling-Edge Interrupt Enable. ...
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C8051F330/1, C8051F330D Table 8.1. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD Parameter Response Time: * Mode 0, Vcm = 1.5 V Response Time: * Mode 1, Vcm = 1.5 V Response Time: ...
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CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...
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C8051F330/1, C8051F330D With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- ...
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Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc- tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary ...
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C8051F330/1, C8051F330D Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic DEC Rn Decrement register DEC direct Decrement direct byte DEC @Ri Decrement indirect RAM INC DPTR Increment Data Pointer MUL AB Multiply A and B DIV AB Divide A by ...
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Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic MOV direct, #data Move immediate to direct byte MOV @Ri, A Move A to indirect RAM MOV @Ri, direct Move direct byte to indirect RAM MOV @Ri, #data Move immediate to indirect ...
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C8051F330/1, C8051F330D Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic JNZ rel Jump if A does not equal zero CJNE A, direct, rel Compare direct byte to A and jump if not equal CJNE A, #data, rel Compare immediate to ...
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Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but ...
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C8051F330/1, C8051F330D 9.2.2. Data Memory The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ...
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Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a ...
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C8051F330/1, C8051F330D Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description ADC0LTH 0xC6 ADC0 Less-Than Compare Word High ADC0LTL 0xC5 ADC0 Less-Than Compare Word Low AMX0N 0xBA AMUX0 ...
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Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description PCA0CPM1 0xDB PCA Module 1 Mode Register PCA0CPM2 0xDC PCA Module 2 Mode Register PCA0H 0xFA PCA Counter High ...
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C8051F330/1, C8051F330D 9.2.7. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in ...
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R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction cleared to logic 0 by all other ...
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C8051F330/1, C8051F330D R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7-0: ACC: Accumulator. This register is the accumulator for arithmetic operations. R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7- Register. This register serves as a ...
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Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 13 interrupt sources with two prior- ity levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version ...
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C8051F330/1, C8051F330D 9.3.2. External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high ...
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Table 9.4. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 0x0003 (/INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (/INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B RESERVED 0x0043 ...
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C8051F330/1, C8051F330D 9.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions ...
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R R/W R/W - PSPI0 PT2 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 1, Write = don't care. Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set ...
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C8051F330/1, C8051F330D R/W R/W R/W ET3 Reserved ECP0 Bit7 Bit6 Bit5 Bit7: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L ...
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R/W R/W R/W PT3 Reserved PCP0 Bit7 Bit6 Bit5 Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set ...
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C8051F330/1, C8051F330D R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to Figure 18.4 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 input is active high. Bits6-4: ...
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Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter- rupts and ...
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C8051F330/1, C8051F330D 9.4.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc- tion that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all ...
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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their ...
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C8051F330/1, C8051F330D 10.1. Power-On Reset During power-up, the device is held in a reset state and the /RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the ...
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Power-Fail Reset/V DD When a power-down transition or power irregularity causes monitor will drive the /RST pin low and hold the CIP- reset state (see Figure 10.2). When returns to a level above V , the CIP-51 ...
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C8051F330/1, C8051F330D 10.3. External Reset The external /RST pin provides a means for external circuitry to force the device into a reset state. Assert- ing an active-low signal on the /RST pin generates a reset; an external pull-up and/or decoupling ...
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Software Reset Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol- lowing a software forced reset. The state of the /RST pin is unaffected by this reset. ...
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C8051F330/1, C8051F330D Table 10.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter I OL /RST Output Low Voltage V /RST Input High Voltage /RST Input Low Voltage /RST Input Pullup Current /RST = 0 ...
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Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft- ware using the MOVX ...
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C8051F330/1, C8051F330D 11.1.3. Flash Write Procedure Flash bytes are programmed by software with the following sequence: Step 1. Disable interrupts (recommended). Step 2. Erase the 512-byte Flash page containing the target location, as described in 11.1.2. Step 3. Set the ...
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Non-volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX ...
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C8051F330/1, C8051F330D The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user ...
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Bit7 Bit6 Bit5 Bits7-2: UNUSED: Read = 000000b, Write = don’t care. Bit1: PSEE: Program Store Erase Enable Setting this bit (in combination with PSWE) allows an entire page of Flash program memory to ...
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C8051F330/1, C8051F330D R/W R/W R/W FOSE Reserved Reserved Reserved Reserved Reserved Reserved Reserved 10000000 Bit7 Bit6 Bit5 Bit7: FOSE: Flash One-shot Enable This bit enables the Flash read one-shot. When the Flash one-shot disabled, the Flash sense amps are enabled ...
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External RAM The C8051F330/1, C8051F330D devices include 512 bytes of RAM mapped into the external data mem- ory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or ...
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C8051F330/1, C8051F330D 102 Rev. 1.2 ...
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Oscillators C8051F330/1, C8051F330D devices include a programmable internal high-frequency oscillator, a pro- grammable internal low-frequency oscillator, and an external oscillator drive circuit. The internal high-fre- quency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as ...
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C8051F330/1, C8051F330D R R/W R/W - Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0. Write = don’t care. Bits 6-0: OSCICL: Internal Oscillator Calibration Register. This register determines the internal oscillator period. When set to 0000000b, the H-F oscil- lator ...
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Programmable Internal Low-Frequency (L-F) Oscillator All C8051F330/1, C8051F330D devices include a programmable low-frequency internal oscillator, which is calibrated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the ...
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C8051F330/1, C8051F330D 13.3. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- ...
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R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal Oscillator is running and stable. Bits6-4: XOSCMD2-0: ...
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C8051F330/1, C8051F330D 13.3.1. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 1. The External Oscillator Frequency Control value ...
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Capacitor values depend on crystal specifications Figure 13.6. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram C8051F330/1, C8051F330D XTAL1 XTAL2 22pF* Rev. 1.2 109 ...
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C8051F330/1, C8051F330D 13.3.2. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 2. The capacitor should be no greater than 100 ...
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System Clock Selection The CLKSL bits in register OSCICN select which oscillator is used as the system clock. CLKSL0 must be set to ‘1’ for the system clock to run from the external oscillator; however the external oscillator may ...
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C8051F330/1, C8051F330D Table 13.1. Internal Oscillator Electrical Characteristics V = 2 –40 to +85 °C unless otherwise specified DD A Parameter Internal High-Frequency Oscillator (Using Factory-Calibrated Settings) Oscillator Frequency IFCN = 11b 25 °C, Oscillator ...
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Port Input/Output Digital and analog resources are available through 17 I/O pins. Port pins are organized as two byte-wide Ports and one 1-bit Port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input; ...
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C8051F330/1, C8051F330D /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT Analog Select ANALOG INPUT PORT-INPUT Figure 14.2. Port I/O Cell Block Diagram 114 VDD VDD (WEAK) GND Rev. 1.2 PORT PAD ...
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Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 14.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding ...
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C8051F330/1, C8051F330D SF Signals VREF IDA x1 x2 PIN I TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI P0SKIP[7:0] Port pin potentially available ...
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Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or ...
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C8051F330/1, C8051F330D CP0AE Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP0AE: Comparator0 Asynchronous Output Enable 0: Asynchronous CP0 unavailable at Port pin. 1: Asynchronous CP0 routed to Port pin. ...
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R/W R/W R/W WEAKPUD XBARE T1E Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input). 1: Weak Pull-ups disabled. Bit6: XBARE: Crossbar Enable. 0: Crossbar ...
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C8051F330/1, C8051F330D 14.3. General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports2-0 are accessed through corresponding special function registers (SFRs) that are ...
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R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Output Configuration Bits for P0.7-P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. (Note: When SDA and ...
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C8051F330/1, C8051F330D R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Analog Input Configuration Bits for P1.7-P1.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P1.n pin is configured as an ...
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Bit7 Bit6 Bit5 Bits7-1: Unused. Read = 0000000b. Write = don’t care. Bit0: P2.0 Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance ...
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C8051F330/1, C8051F330D Table 14.1. Port I/O DC Electrical Characteristics V = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters I = –3 mA, Port I/O push-pull –10 µA, Port I/O push-pull Output ...
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SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I the interface by the system controller are byte oriented with the ...
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C8051F330/1, C8051F330D 15.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: 1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor. ...
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SMBus Operation Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device initiates both ...
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C8051F330/1, C8051F330D 15.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with ...
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Using the SMBus The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con- trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides the following application-independent ...
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C8051F330/1, C8051F330D 15.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, ...
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Figure 15.4 shows the typical SCL generation described by Equation 15.2. Notice that T twice as large The actual SCL output may vary due to other devices on the bus (SCL may be LOW extended low by ...
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C8051F330/1, C8051F330D R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins. 0: SMBus interface disabled. 1: SMBus interface ...
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SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see Figure 15.6). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump ...
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C8051F330/1, C8051F330D R R R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: SMBus operating in Master Mode. ...
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Table 15.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: MASTER • A START is generated. • START is generated. TXMODE • SMB0DAT is written before the start of an SMBus frame. • A START followed by ...
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C8051F330/1, C8051F330D 15.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag ...
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SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. ...
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C8051F330/1, C8051F330D 15.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and ...
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Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and ...
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C8051F330/1, C8051F330D 15.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a ...
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SMBus Status Decoding The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the shown response ...
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C8051F330/1, C8051F330D Table 15.4. SMBus Status Decoding Values Read Current SMbus State A master data byte was received; 1000 slave byte was transmitted slave byte was transmitted; 0100 ...
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Table 15.4. SMBus Status Decoding Values Read Current SMbus State A slave address was received Lost arbitration as master; slave 0010 address received; ACK Lost arbitration while attempting a 0010 Lost ...
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C8051F330/1, C8051F330D 144 Rev. 1.2 ...
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UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “16.1. ...
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C8051F330/1, C8051F330D 16.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX ...
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Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below. Figure 16.3. UART Interconnect Diagram 16.2.1. 8-Bit UART 8-Bit UART ...
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C8051F330/1, C8051F330D 16.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth ...
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Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it ...
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C8051F330/1, C8051F330D R/W R R/W S0MODE - MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. Bit6: ...
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R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SBUF0[7:0]: Serial Data Buffer Bits 7-0 (MSB-LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift ...
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C8051F330/1, C8051F330D Table 16.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 -0.32% 115200 -0.32% 57600 0.15% 28800 -0.32% 14400 0.15% 9600 -0.32% 2400 -0.32% 1200 0.15% Notes: 1. ...
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Table 16.3. Timer Settings for Standard Baud Rates Using an External Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% 115200 0.00% ...
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C8051F330/1, C8051F330D Table 16.4. Timer Settings for Standard Baud Rates Using an External Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% ...
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Table 16.5. Timer Settings for Standard Baud Rates Using an External Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% 115200 0.00% ...
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C8051F330/1, C8051F330D Table 16.6. Timer Settings for Standard Baud Rates Using an External Oscillator Target Baud Baud Rate Rate% (bps) Error 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% 115200 ...
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Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple ...
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C8051F330/1, C8051F330D 17.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 17.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to ...
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SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data ...
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C8051F330/1, C8051F330D Master Device 1 Figure 17.2. Multiple-Master Mode Connection Diagram Master Device Figure 17.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram Master Device GPIO Figure 17.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram ...
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SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave slave, bytes are shifted in through the MOSI pin and out through the MISO pin by ...
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C8051F330/1, C8051F330D 17.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used ...
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SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=1, CKPHA=0) MOSI MSB Bit 6 MISO MSB Bit 6 NSS (4-Wire Mode) Figure 17.6. Slave Mode Data/Clock Timing (CKPHA = 0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=1) MOSI MSB MISO MSB NSS (4-Wire Mode) Figure ...
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C8051F330/1, C8051F330D 17.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers ...
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R/W R/W R/W SPIF WCOL MODF RXOVRN NSSMD1 NSSMD0 Bit7 Bit6 Bit5 Bit 7: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this ...
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C8051F330/1, C8051F330D R/W R/W R/W SCR7 SCR6 SCR5 Bit7 Bit6 Bit5 Bits 7-0: SCR7-SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency ...
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SCK* T MCKH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 17.12. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is ...
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C8051F330/1, C8051F330D NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 17.14. SPI Slave Timing (CKPHA = 0) NSS T SE ...
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Table 17.1. SPI Slave Timing Parameters Parameter Description * Master Mode Timing (See Figure 17.12 and Figure 17.13) T SCK High Time MCKH T SCK Low Time MCKL T MISO Valid to SCK Shift Edge MIS T SCK Shift Edge ...
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C8051F330/1, C8051F330D 170 Rev. 1.2 ...
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Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can be ...
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C8051F330/1, C8051F330D The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to “14.1. Priority Crossbar Decoder” on page ...
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Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter ...
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C8051F330/1, C8051F330D 18.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits ...
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R/W R/W R/W TF1 TR1 TF0 Bit7 Bit6 Bit5 Bit7: TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto- matically cleared when the CPU vectors to the ...
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C8051F330/1, C8051F330D R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND ...
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R/W R/W R/W T3MH T3ML T2MH Bit7 Bit6 Bit5 Bit7: T3MH: Timer 3 High Byte Clock Select. This bit selects the clock supplied to the Timer 3 high byte if Timer 3 is configured in split 8- bit timer mode. ...
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C8051F330/1, C8051F330D R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. Figure 18.7. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 ...
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Timer 2 Timer 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines the ...
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C8051F330/1, C8051F330D 18.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 18.12. TMR2RLL holds the reload value for ...
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R/W R/W R/W TF2H TF2L TF2LEN Bit7 Bit6 Bit5 Bit7: TF2H: Timer 2 High Byte Overflow Flag. Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00 bit mode, this will occur when Timer ...
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C8051F330/1, C8051F330D R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. Figure 18.14. TMR2RLL: Timer 2 Reload Register Low Byte R/W R/W ...
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Timer 3 Timer 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines the ...
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C8051F330/1, C8051F330D 18.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TH3 and TL3). Both 8-bit timers operate in auto-reload mode as shown in Figure 18.12. TMR3RLL holds the reload value for TL3; ...
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R/W R/W R/W TF3H TF3L TF3LEN Bit7 Bit6 Bit5 Bit7: TF3H: Timer 3 High Byte Overflow Flag. Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00 bit mode, this will occur when Timer ...
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C8051F330/1, C8051F330D R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TMR3RLL: Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the reload value for Timer 3. Figure 18.21. TMR3RLL: Timer 3 Reload Register Low Byte R/W R/W ...
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Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. Each capture/compare module has ...
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C8051F330/1, C8051F330D 19.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value ...
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Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator. Each module has Special Function ...
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C8051F330/1, C8051F330D 19.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). ...
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Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and ...
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C8051F330/1, C8051F330D 19.2.3. High-Speed Output Mode In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, and ...
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Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out- put is toggled. The frequency of ...
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C8051F330/1, C8051F330D 19.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated (PWM) output on its associ- ated CEXn pin. The frequency of the output is dependent on the timebase for the ...
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Pulse Width Modulator Mode A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare mod- ule defines the number of PCA clocks for the low time of the PWM signal. When ...
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C8051F330/1, C8051F330D 19.3. Watchdog Timer Mode A programmable watchdog timer (WDT) function is available through the PCA Module 2. The WDT is used to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a ...
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Note that the 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This offset value is the number of PCA0L overflows before a reset 256 PCA clocks may pass before the ...
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C8051F330/1, C8051F330D Table 19.3. Watchdog Timer Timeout Intervals System Clock (Hz) 24,500,000 24,500,000 24,500,000 18,432,000 18,432,000 18,432,000 11,059,200 11,059,200 11,059,200 3,060,000 3,060,000 3,060,000 32,000 32,000 32,000 Notes: 1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value of ...
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Register Descriptions for PCA Following are detailed descriptions of the special function registers related to the operation of the PCA. R/W R Bit7 Bit6 Bit5 Bit7: CF: PCA Counter/Timer Overflow Flag. Set by hardware when ...
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C8051F330/1, C8051F330D R/W R/W R/W CIDL WDTE WDLCK Bit7 Bit6 Bit5 Bit7: CIDL: PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode. 0: PCA continues to function normally while the system controller is in Idle Mode. ...