C8051F331 Silicon Laboratories Inc, C8051F331 Datasheet - Page 91

• Manufacturer Part Number: C8051F331
• Description: IC 8051 MCU 8K FLASH 20MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F331

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

10.2. Power-Fail Reset/V
When a power-down transition or power irregularity causes
monitor will drive the /RST pin low and hold the CIP-51 in a reset state (see Figure 10.2). When
returns to a level above V
nal data memory contents are not altered by the power-fail reset, it is impossible to determine if
dropped below the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be
valid. The
not altered by any other reset source. For example, if the
performed, the
Important Note: The
V
dure for configuring the
See Figure 10.2 for
reset. See Table 10.1 for complete electrical characteristics of the
DD monitor as a reset source before it is enabled and stabilized may cause a system reset. The proce-
Bit7:
Bit6:
Bits5-0:
VDMEN
R/W
Bit7
Step 1. Enable the
Step 2. Wait for the
Step 3. Select the
V
VDMEN:
This bit is turns the
resets until it is also selected as a reset source in register RSTSRC (Figure 10.4). The VDD
Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the
VDD monitor as a reset source before it has stabilized may generate a system reset.
See Table 10.1 for the minimum VDD Monitor turn-on time.
0:
1:
V
This bit indicates the current power supply status (
0:
1:
Reserved. Read = 000000b. Write = don’t care.
DD monitor is disabled after power-on resets; however its defined state (enabled/disabled) is
DD STAT:
VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved
V
V
V
V
V
DD Monitor Disabled.
DD Monitor Enabled.
DD is at or below the
DD is above the
DD monitor will still be enabled after the reset.
Bit6
R
V
V
V
DD monitor timing; note that the reset delay is not incurred after a
DD Monitor Enable.
DD monitor must be enabled before it is selected as a reset source. Selecting the
V
V
RST
DD monitor as a reset source is shown below:
DD Status.
V
V
V
, the CIP-51 will be released from the reset state. Note that even though inter-
DD monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
Bit5
DD monitor (VDMEN bit in VDM0CN = ‘1’).
Figure 10.3. VDM0CN:
DD monitor to stabilize (see Table 10.1 for the
R
V
DD
V
DD monitor circuit on/off. The
DD monitor threshold.
Monitor
V
DD monitor threshold.
Bit4
R
C8051F330/1, C8051F330D
Rev. 1.2
Bit3
R
V
DD Monitor Control
V
DD monitor is enabled and a software reset is
V
V
DD to drop below V
Bit2
V
R
DD Monitor output).
DD Monitor cannot generate system
V
DD monitor.
Bit1
R
V
DD Monitor turn-on time).
SFR Address:
RST
Bit0
, the power supply
R
V
0xFF
DD monitor
Reset Value
Variable
V
V
DD
DD
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