C8051F331 Silicon Laboratories Inc, C8051F331 Datasheet - Page 73

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C8051F331

Manufacturer Part Number
C8051F331
Description
IC 8051 MCU 8K FLASH 20MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Datasheet

Specifications of C8051F331

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-

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0
9.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.2 lists the SFRs imple-
mented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in Table 9.3,
for a detailed description of each register.
Table 9.2. Special Function Register (SFR) Memory Map
Table 9.3. Special Function Registers
D8 PCA0CN
D0
C8 TMR2CN
C0 SMB0CN
F8
F0
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
E0
B8
B0
A8
A0
98
90
88
80
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
ACC
ADC0CF
ADC0CN
ADC0GTH
ADC0GTL
ADC0H
ADC0L
(bit addressable)
SPI0CN
SCON0
TCON
PSW
ACC
0(8)
P2
P1
P0
IP
IE
B
Address
OSCXCN
SPI0CFG
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
TMR3CN
REF0CN
SMB0CF
P0MDIN
CLKSEL
IDA0CN
PCA0L
SBUF0
TMOD
0xBC
0xBD
0xC4
0xC3
0xBE
XBR0
0xE0
0xE8
1(9)
SP
SMB0DAT
TMR2RLL TMR2RLH
TMR3RLL TMR3RLH
SPI0CKR
OSCICN
P1MDIN
EMI0CN
Description
Accumulator
ADC0 Configuration
ADC0 Control
ADC0 Greater-Than Compare High
ADC0 Greater-Than Compare Low
ADC0 High
ADC0 Low
AMX0N
PCA0H
XBR1
DPL
2(A)
TL0
PCA0CPL0 PCA0CPH0
ADC0GTL ADC0GTH
OSCLCN
SPI0DAT
CPT0CN
OSCICL
AMX0P
DPH
3(B)
TL1
C8051F330/1, C8051F330D
Rev. 1.2
P0MDOUT P1MDOUT P2MDOUT
ADC0CF
P0SKIP
IT01CF
TMR2L
TMR3L
TH0
4(C)
ADC0LTL
CPT0MD
P1SKIP
TMR2H
TMR3H
ADC0L
TH1
5(D)
ADC0LTH
CKCON
ADC0H
FLSCL
IDA0L
EIP1
EIE1
6(E)
VDM0CN
RSTSRC
CPT0MX
FLKEY
PSCTL
IDA0H
PCON
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7(F)
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