MC908AZ60AVFU Freescale Semiconductor, MC908AZ60AVFU Datasheet - Page 56

• Manufacturer Part Number: MC908AZ60AVFU
• Description: IC MCU 61K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AVFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FLASH-1 Memory
4.6 FLASH-1 Page Erase Operation
Use this step-by-step procedure to erase a page (128 bytes) of FLASH-1 memory to read as logic 1:
4.7 FLASH-1 Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes with
address ranges as follows:
During the programming cycle, make sure that all addresses being written to fit within one of the ranges
specified above. Attempts to program addresses in different row ranges in one programming cycle will fail.
Use this step-by-step procedure to program a row of FLASH-1 memory.
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10. Wait for a time, t
1. Set the ERASE bit and clear the MASS bit in the FLASH-1 Control Register (FL1CR).
2. Read the FLASH-1 Block Protect Register (FL1BPR).
3. Write any data to any FLASH-1 address within the address range of the page (128 byte block) to
4. Wait for time, t
5. Set the HVEN bit.
6. Wait for time, t
7. Clear the ERASE bit.
8. Wait for time, t
9. Clear the HVEN bit.
1. Set the PGM bit in the FLASH-1 Control Register (FL1CR). This configures the memory for
2. Read the FLASH-1 Block Protect Register (FL1BPR).
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be erased.
$XX00 to $XX3F
$XX40 to $XX7F
$XX80 to $XXBF
$XXC0 to $XXFF
program operation and enables the latching of address and data programming.
A. Programming and erasing of FLASH locations can not be performed by
code being executed from the same FLASH array.
B. While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
however to ensure that these operations do not access any address within
the FLASH array memory space such as the COP Control Register
(COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during
program/erase operations.
In order to avoid program disturbs, the row must be erased before any byte
on that row is programmed.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
NVS
ERASE
NVH
RCV
.
.
, after which the memory can be accessed in normal read mode.
.
NOTE
NOTE
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