MC9S08DZ32ACLH Freescale Semiconductor, MC9S08DZ32ACLH Datasheet - Page 53

• Manufacturer Part Number: MC9S08DZ32ACLH
• Description: IC MCU 32K FLASH 2K RAM 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ32ACLH

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: S08DZ
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, I2C, SCI, SPI
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 5.5 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• On-chip Adc: 12 bit, 24 channel
• For Use With: EVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.5.2
Before any program or erase command can be accepted, the Flash and EEPROM clock divider register
(FCDIV) must be written to set the internal clock for the Flash and EEPROM module to a frequency
(f
Register
reset initialization. The user must ensure that FACCERR is not set before writing to the FCDIV register.
One period of the resulting clock (1/f
pulses. An integer number of these timing pulses is used by the command processor to complete a program
or erase command.
Table 4-6
of FCLK (f
of cycles of FCLK and as an absolute time for the case where t
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
4.5.3
The FCDIV register must be initialized after any reset and any error flag is cleared before beginning
command execution. The command execution steps are:
Freescale Semiconductor
FCLK
•
•
1. Write a data value to an address in the Flash or EEPROM array. The address and data information
) between 150 kHz and 200 kHz (see
Burst programming capability
Sector erase abort
from this write is latched into the Flash and EEPROM interface. This write is a required first step
in any command sequence. For erase and blank check commands, the value of the data is not
important. For sector erase commands, the address can be any address in the sector of Flash or
EEPROM to be erased. For mass erase and blank check commands, the address can be any address
in the Flash or EEPROM memory. Flash and EEPROM erase independently of each other.
(FCDIV)”). This register can be written only once, so normally this write is performed during
shows program and erase times. The bus clock frequency and FCDIV determine the frequency
FCLK
Program and Erase Times
Program and Erase Command Execution
1
Excluding start/end overhead
). The time for one cycle of FCLK is t
Sector erase abort
Burst program
Byte program
Sector erase
Mass erase
Parameter
Table 4-6. Program and Erase Times
MC9S08DZ60 Series Data Sheet, Rev. 4
FCLK
) is used by the command processor to time program and erase
Section 4.5.11.1, “Flash and EEPROM Clock Divider
Cycles of FCLK
20,000
4000
9
4
4
FCLK
= 1/f
FCLK
FCLK
Time if FCLK = 200 kHz
= 5 μs. Program and erase times
. The times are shown as a number
100 ms
20 μs
20 μs
20 ms
45 μs
1
1
Chapter 4 Memory
53