SAF-XC164S-16F20F BB Infineon Technologies, SAF-XC164S-16F20F BB Datasheet
SAF-XC164S-16F20F BB
Specifications of SAF-XC164S-16F20F BB
SP000094296
SP000094298
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SAF-XC164S-16F20F BB Summary of contents
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XC164S-8F/ ...
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... Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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XC164S-8F/ ...
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XC164S Revision History: V1.2, 2006-08 Previous Version(s): V1.1, 2006-03 V1.0, 2005-01 Page Subjects (major changes since last revision) 6 New derivatives added. 10 Description of the TRST signal modified. 45 Instructions Set Summary improved. 48 Footnote added about pin XTAL1 ...
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Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Single-Chip Microcontroller with C166SV2 Core XC166 Family 1 Summary of Features • High Performance 16-bit CPU with 5-Stage Pipeline – Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution) – 1-Cycle Multiplication (16 × 16 bit), ...
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Programmable External Bus Characteristics for Different Address Ranges – Multiplexed or Demultiplexed External Address/Data Buses – Selectable Address Bus Width – 16-Bit or 8-Bit Data Bus Width – Four Programmable Chip-Select Signals • General Purpose I/O ...
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... Range -40 °C to SAF-XC164S-16F40F 85 °C -40 °C to SAF-XC164S-16F20F 85 °C -40 °C to SAF-XC164S-8F40F 85 °C -40 °C to SAF-XC164S-8F20F 85 °C SAF-XC164S-16R40F -40 ° °C SAF-XC164S-16R20F -40 ° °C -40 °C to SAF-XC164S-8R40F 85 °C -40 °C to SAF-XC164S-8R20F 85 °C 1) This Data Sheet is valid for devices starting with and including design step BB. Data Sheet Program On-Chip RAM ...
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General Device Information 2.1 Introduction The XC164S derivatives are high-performance members of the Infineon XC166 Family of full featured single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), ...
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Pin Configuration and Definition The pins of the XC164S are described in detail in functions. Figure 2 summarizes all pins in a condensed way, showing their location on the package. E*) mark pins to be used as alternate external ...
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... XC164S. A spike filter suppresses input pulses < 10 ns. Input pulses > 100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 CPU clock cycles. Note: The reset duration must be sufficient to let the hardware configuration signals settle ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp P5. P5. P5.6 26 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp P4.6 59 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. P20 IO P20 P20 P20 P20 P20. Data Sheet Function Port 5-bit bidirectional I/O port. ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. PORT0 IO P0L P0L.7 74 P0H P0L.3 7 P0H P0L.7 78 PORT1 IO P1L.0 79 I/O P1L ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. PORT1 IO (cont’d) P1H I/O P1H I/O P1H I/O P1H I P1H.4 93 I/O I ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. V 35, 97 – DDI V 9, 17, – DDP 38, 61 34, 98 – SSI V 8, 16, – SSP 37, 62, 88 Data Sheet ...
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Functional Description The architecture of the XC164S combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a very well-balanced way. In addition, the on-chip memory blocks allow the design of compact systems-on-silicon with maximum ...
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Memory Subsystem and Organization The memory space of the XC164S is configured in a Von Neumann architecture, which means that all internal and external resources, such as code memory, data memory, registers and I/O ports, are organized within the ...
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R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs). The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR, any location ...
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External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required one of four ...
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Central Processing Unit (CPU) The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and accumulate unit (MAC), a register-file providing three ...
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Also multiplication and most MAC instructions execute in one single cycle. All multiple-cycle instructions have been optimized so that ...
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Interrupt System With an interrupt response time of typically 8 CPU clocks (in case of internal program execution), the XC164S is capable of reacting very fast to the occurrence of non- deterministic events. The architecture of the XC164S supports ...
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Table 4 XC164S Interrupt Nodes Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM ...
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Table 4 XC164S Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request CAPCOM Register 29 CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 ...
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Table 4 XC164S Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request CAPCOM6 Timer T12 CAPCOM6 Timer T13 CAPCOM6 Emergency CAPCOM6 SSC1 Transmit SSC1 Receive SSC1 Error Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node ...
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The XC164S also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...
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On-Chip Debug Support (OCDS) The On-Chip Debug Support system provides a broad range of debug and emulation features built into the XC164S. The user software running on the XC164S can thus be debugged within the target system environment. The ...
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CAPCOM2 module have each one port pin associated with it which serves as an input pin for triggering the capture function output pin to indicate the occurrence of a compare event. ...
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CC T0IN/T7IN T6OUF CCxIO CCxIO CCxIO f CC T6OUF CAPCOM1 provides channels … 15, CAPCOM2 provides channels … 31. (see signals CCxIO and CCxIRQ) Figure 5 CAPCOM1/2 Unit Block Diagram Data Sheet Reload ...
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The Capture/Compare Unit (CAPCOM6) The CAPCOM6 unit supports generation and control of timing sequences three 16-bit capture/compare channels plus one independent 10-bit compare channel. In compare mode the CAPCOM6 unit provides two output signals per channel ...
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General Purpose Timer Unit (GPT12E) The GPT12E unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, ...
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T3CON.BPS1 GPT T2IN T2 Mode Control T2EUD T3 T3IN Mode Control T3EUD T4IN T4 Mode Control T4EUD Figure 7 Block Diagram of GPT1 With its maximum resolution of 2 system clock cycles, the GPT2 module provides ...
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Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, ...
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T6CON.BPS2 GPT T5 T5IN Mode Control CAPIN CAPREL Mode Control T3IN/ T3EUD T6 Mode Control T6IN Figure 8 Block Diagram of GPT2 Data Sheet Basic Clock GPT2 Timer T5 U/D Clear Capture GPT2 CAPREL Reload Clear ...
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Real Time Clock The Real Time Clock (RTC) module of the XC164S is directly clocked via a separate clock driver with the prescaled on-chip main oscillator frequency ( therefore independent from the selected clock generation mode of the XC164S. ...
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The RTC module can be used for different purposes: • System clock to determine the current time and date, optionally during idle mode, sleep mode, and power down mode. • Cyclic time based interrupt, to provide a system time tick ...
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A/D Converter For analog signal measurement, a 10-bit A/D converter with 14 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) ...
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Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) The Asynchronous/Synchronous Serial Interfaces ASC0/ASC1 (USARTs) provide serial communication with other microcontrollers, processors, terminals or external peripheral components. They are upward compatible with the serial ports of the Infineon 8-bit microcontroller families and support full-duplex ...
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High Speed Synchronous Serial Channels (SSC0/SSC1) The High Speed Synchronous Serial Channels SSC0/SSC1 support full-duplex and half- duplex synchronous communication. It may be configured so it interfaces with serially linked peripheral components, full SPI functionality is supported. A dedicated ...
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... Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can be disabled until the EINIT instruction has been executed (compatible mode can be disabled and enabled at any time by executing instructions DISWDT and ENWDT (enhanced mode). Thus, the chip’ ...
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Clock Generation The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers to generate the clock signals for the XC164S with high flexibility. The master clock the reference clock signal, and is used for TwinCAN and is ...
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Table 7 Summary of the XC164S’s Parallel Ports Port Control PORT0 Pad drivers PORT1 Pad drivers Port 3 Pad drivers, Open drain, Input threshold Port 4 Pad drivers, Open drain, Input threshold Port 5 – Port 9 Pad drivers, Open ...
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Power Management The XC164S provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): • Power Saving Modes switch the XC164S ...
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Instruction Set Summary Table 8 lists the instructions of the XC164S in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and ...
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Table 8 Instruction Set Summary (cont’d) Mnemonic Description ROL/ROR Rotate left/right direct word GPR ASHR Arithmetic (sign bit) shift right direct word GPR MOV(B) Move word (byte) data MOVBS/Z Move byte operand to word op. with sign/zero extension JMPA/I/R Jump ...
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Table 8 Instruction Set Summary (cont’d) Mnemonic Description NOP Null operation CoMUL/CoMAC Multiply (and accumulate) CoADD/CoSUB Add/Subtract Co(A)SHR (Arithmetic) Shift right CoSHL Shift left CoLOAD/STORE Load accumulator/Store MAC register CoCMP Compare CoMAX/MIN Maximum/Minimum CoABS/CoRND Absolute value/Round accumulator CoMOV Data move ...
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Electrical Parameters 4.1 General Parameters Table 9 Absolute Maximum Ratings Parameter Storage temperature Junction temperature V Voltage on pins with DDI V respect to ground ( ) SS V Voltage on pins with DDP V respect to ground ( ...
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Operating Conditions The following operating conditions must not be exceeded to ensure correct operation of the XC164S. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 10 Operating Condition Parameters Parameter Digital supply ...
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Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range: input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified ...
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DC Parameters Table 11 DC Characteristics (Operating Conditions apply) Parameter Symbol V Input low voltage TTL (all except XTAL1) V Input low voltage 2) XTAL1 V Input low voltage (Special Threshold) V Input high voltage TTL (all except XTAL1) ...
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Table 11 DC Characteristics (Operating Conditions apply) Parameter Symbol I Level inactive hold 13) current I Level active hold 13) current I XTAL1 input current 14) C Pin capacitance (digital inputs/outputs) 1) Keeping signal levels within the limits specified in ...
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output current above | OXnom For any group of 16 neighboring port output pins the total output current in each direction (Σ remain below 50 mA. Table 13 Power Consumption XC164S (Operating Conditions apply) Parameter Power supply ...
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I [mA] 140 120 100 Figure 10 Supply/Idle Current as a Function of Operating Frequency Data Sheet XC164S Derivatives Electrical Parameters I DDImax I DDItyp I IDXmax I IDXtyp 40 f [MHz] ...
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I [mA] 3.0 2.0 1.0 4 Figure 11 Sleep and Power Down Supply Current due to RTC and Oscillator Running Function of Oscillator Frequency I PDL [mA] 1.5 1.0 0.5 -50 0 Figure 12 Sleep and Power Down ...
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Analog/Digital Converter Parameters Table 14 A/D Converter Characteristics (Operating Conditions apply) Parameter Analog reference supply Analog reference ground Analog input voltage range Basic clock frequency Conversion time for 10-bit 4) result Conversion time for 8-bit 4) result Calibration time ...
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The limit values for must not be exceeded when selecting the peripheral frequency and the ADCTC setting This parameter includes the sample time result register with the conversion result ( t Values for the basic clock ...
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Sample time and conversion time of the XC164S’s A/D Converter are programmable. In compatibility mode, the above timing can be calculated using f The limit values for must not be exceeded when selecting ADCTC. BC Table 15 A/D Converter Computation ...
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AC Parameters 4.4.1 Definition of Internal Timing The internal operation of the XC164S is controlled by the internal master clock The master clock signal different mechanisms. The duration of master clock periods (TCMs) and their variation (and also the ...
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CPU and EBC are clocked with the CPU clock signal same frequency as the master clock ( f f two This factor is selected by bit CPSYS in register SYSCON1. CPU MC The specification of the external ...
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PLL jitter is negligible. The value of the accumulated PLL jitter depends on the number of consecutive VCO output cycles within the respective timeframe. The VCO output clock is ...
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Table 16 VCO Bands for PLL Operation PLLCON.PLLVB VCO Frequency Range 00 100 … 150 MHz 01 150 … 200 MHz 10 200 … 250 MHz 11 Reserved 1) Not subject to production test - verified by design/characterization. Data Sheet ...
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On-chip Flash Operation The XC164S’s Flash module delivers data within a fixed access time (see Accesses to the Flash module are controlled by the PMI and take 1+WS clock cycles, where WS is the number of Flash access waitstates ...
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External Clock Drive XTAL1 Table 19 External Clock Drive Characteristics (Operating Conditions apply) Parameter Oscillator period 2) High time 2) Low time 2) Rise time 2) Fall time 1) The maximum limit is only relevant for PLL operation to ...
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Testing Waveforms Output delay Hold time 2.0 V 0.8 V 0.45 V Output timings refer to the rising edge of CLKOUT. Input timings are calculated from the time, when the input signal reaches respectively. IH ...
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External Bus Timing Table 20 CLKOUT Reference Signal Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time 1) The CLKOUT cycle time is influenced by the PLL jitter (given values apply to ...
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Variable Memory Cycles External bus cycles of the XC164S are executed in five subsequent cycle phases (AB F). The duration of each cycle phase is programmable (via the TCONCSx registers) to adapt the external bus cycles to ...
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External Bus Cycle Timing (Operating Conditions apply) Table 22 Parameter Output valid delay for: RD, WR(L/H) Output valid delay for: BHE, ALE Output valid delay for: A23 … A16, A15 … A0 (on PORT1) Output valid delay for: A15 … ...
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CLKOUT tc 11 ALE tc 11 A23-A16, BHE, CSx RD WR(L/H) tc AD15-AD0 (read) tc AD15-AD0 (write) Figure 20 Multiplexed Bus Cycle Data Sheet High Address ...
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CLKOUT tc 11 ALE tc 11 A23-A0, BHE, CSx RD WR(L/H) D15-D0 (read) D15-D0 (write) Figure 21 Demultiplexed Bus Cycle Data Sheet Address XC164S ...
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Package and Reliability 5.1 Packaging Table 23 Package Parameters Parameter Green Package PG-TQFP-100-5 Thermal resistance junction to case Thermal resistance junction to leads Standard Package P-TQFP-100-16 Thermal resistance junction to case Thermal resistance junction to leads Data Sheet Symbol ...
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Package Outlines 0 0 0.22 ±0.05 0. 100 1 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side Figure 22 PG-TQFP-100-5 (Plastic Green Thin Quad ...
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Figure 23 P-TQFP-100-16 (Plastic Thin Quad Flat Package) You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet Package and Reliability 73 XC164S Derivatives GPP09189 Dimensions in mm V1.2, ...
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Flash Memory Parameters The data retention time of the XC164S’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Table 24 ...
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