MC33074ADR2G ON Semiconductor, MC33074ADR2G Datasheet - Page 10

• Manufacturer Part Number: MC33074ADR2G
• Description: IC OPAMP QUAD 4.5MHZ 14SOIC
• Manufacturer: ON Semiconductor
• Type: General Purpose Amplifierr

Specifications of MC33074ADR2G

• Amplifier Type: General Purpose
• Number Of Circuits: 4
• Slew Rate: 13 V/µs
• Gain Bandwidth Product: 4.5MHz
• Current - Input Bias: 100nA
• Voltage - Input Offset: 500µV
• Current - Supply: 1.9mA
• Current - Output / Channel: 30mA
• Voltage - Supply, Single/dual (±): 3 V ~ 44 V, ±1.5 V ~ 22 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Rail/rail I/o Type: No
• Number Of Elements: 4
• Unity Gain Bandwidth Product: 4.5MHz
• Common Mode Rejection Ratio: 80dB
• Input Offset Voltage: 3@5VmV
• Input Bias Current: 500nA
• Single Supply Voltage (typ): 5/9/12/15/18/24/28V
• Voltage Gain In Db: 100dB
• Power Supply Rejection Ratio: 80dB
• Power Supply Requirement: Single/Dual
• Shut Down Feature: No
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 44V
• Dual Supply Voltage (min): ±1.5V
• Dual Supply Voltage (max): ±22V
• Technology: Bipolar
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Number Of Channels: 4
• Voltage Gain Db: 100 dB
• Common Mode Rejection Ratio (min): 80 dB
• Input Voltage Range (max): Positive Rail - 1.8 V
• Input Voltage Range (min): Negative Rail
• Operating Supply Voltage: 44 V
• Supply Current: 7.6 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Dual Supply Voltage: +/- 22 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Compliant
• Other names: MC33074ADR2GOS; MC33074ADR2GOS; MC33074ADR2GOSTR

MC34071 amplifier series are similar to op amp products
utilizing JFET input devices, these amplifiers offer other
additional distinct advantages as a result of the PNP
transistor differential input stage and an all NPN transistor
output stage.
stage includes the V
feasible to as low as 3.0 V with the common mode input
voltage at ground potential.
to ±44 V, provided the maximum input voltage range is not
exceeded. Specifically, the input voltages must range
between V
maximum rating table. In practice, although not
recommended, the input voltages can exceed the V
voltage by approximately 3.0 V and decrease below the V
voltage by 0.3 V without causing product damage, although
output phase reversal may occur. It is also possible to source
120
100
Although the bandwidth, slew rate, and settling time of the
Since the input common mode voltage range of this input
The input stage also allows differential input voltages up
9.0
8.0
7.0
6.0
5.0
4.0
80
60
40
20
0
Figure 36. Channel Separation versus Frequency
10
0
V
V
T
A
CC
EE
EE
= 25°C
= -15 V
= +15 V
Figure 34. Supply Current versus
20
and V
5.0
V
CC
EE
30
f, FREQUENCY (kHz)
CC
, |V
Supply Voltage
potential, single supply operation is
EE
supply voltages as shown by the
T
T
10
|, SUPPLY VOLTAGE (V)
A
A
= -55°C
= 125°C
T
50
A
CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
= 25°C
15
70
100
APPLICATIONS INFORMATION
Quad device
20
200
http://onsemi.com
300
25
CC
EE
10
up to approximately 5.0 mA of current from V
either inputs clamping diode without damage or latching,
although phase reversal may again occur.
voltage limit, the amplifier output is readily predictable and
may be in a low or high state depending on the existing input
bias conditions.
geometry input device is substantially lower (2.5 pF) than
the typical JFET input gate capacitance (5.0 pF), better
frequency response for a given input source resistance can
be achieved using the MC34071 series of amplifiers. This
performance feature becomes evident, for example, in fast
settling D−to−A current to voltage conversion applications
where the feedback resistance can form an input pole with
the input capacitance of the op amp. This input pole creates
a 2nd order system with the single pole op amp and is
therefore detrimental to its settling time. In this context,
lower input capacitance is desirable especially for higher
70
60
50
40
30
20
10
105
0
95
85
75
65
10
If one or both inputs exceed the upper common mode
Since the input capacitance associated with the small
-55
Figure 37. Input Noise versus Frequency
-PSR
-25
Figure 35. Power Supply Rejection
+PSR = 20 Log
-PSR = 20 Log
(DV
100
EE
T
Current
A
= +1.5 V)
, AMBIENT TEMPERATURE (°C)
Voltage
0
f, FREQUENCY (kHz)
versus Temperature
DV
DV
25
1.0 k
DV
DV
O
O
+PSR
/A
/A
CC
EE
DM
DM
50
(DV
CC
V
V
V
T
A
CC
EE
CM
10 k
= +1.5 V)
= 25°C
= -15 V
= +15 V
= 0
75
-
A
+
DM
V
V
DV
DV
CC
EE
CC
EE
100
= +15 V
= -15 V
EE
100 k
DV
through
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
O
125