MAX691ACWE+ Maxim Integrated Products, MAX691ACWE+ Datasheet - Page 8

• Manufacturer Part Number: MAX691ACWE+
• Description: IC MPU SUPERVISOR CIRCUIT 16SOIC
• Manufacturer: Maxim Integrated Products
• Type: Battery Backup Circuitr

Specifications of MAX691ACWE+

• Number Of Voltages Monitored: 1
• Output: Push-Pull, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 4.65V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Monitored Voltage: 0 V to 5.5 V
• Undervoltage Threshold: 4.5 V
• Overvoltage Threshold: 4.75 V
• Manual Reset: No
• Watchdog: Yes
• Battery Backup Switching: Yes
• Power-up Reset Delay (typ): 280 ms
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 0 V
• Supply Current (typ): 100 uA
• Maximum Power Dissipation: 762 mW
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 70 C
• Chip Enable Signals: Yes
• Minimum Operating Temperature: 0 C
• Output Type: Active High or Active Low or Open Drain
• Power Fail Detection: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RESET and RESET are asserted when V
the reset threshold (4.65V for the MAX691A/MAX800L,
4.4V for the MAX693A/MAX800M) and remain asserted
for 200ms typ after V
on power-up (Figure 5). The devices’ battery-
switchover comparator does not affect reset assertion.
However, both reset outputs are asserted in battery-
backup mode since V
threshold to enter this mode.
The watchdog monitors µP activity via the Watchdog
Input (WDI). If the µP becomes inactive, RESET and
RESET are asserted. To use the watchdog function,
connect WDI to a bus line or µP I/O line. If WDI
remains high or low for longer than the watchdog time-
out period (1.6s nominal), WDO, RESET, and RESET
are asserted (see RESET and RESET Outputs section,
and the Watchdog Output discussion on this page).
A change of state (high to low, low to high, or a mini-
mum 100ns pulse) at the WDI during the watchdog
period resets the watchdog timer. The watchdog
default timeout is 1.6s.
To disable the watchdog function, leave WDI floating.
An internal resistor network (100kΩ equivalent imped-
ance at WDI) biases WDI to approximately 1.6V.
Internal comparators detect this level and disable the
watchdog timer. When V
old, the watchdog function is disabled and WDI is dis-
connected from its internal resistor network, thus
becoming high impedance.
Microprocessor Supervisory Circuits
Figure 1. Adding an external pulldown resistor ensures
–
R
8
—
E
—
S
—
_______________________________________________________________________________________
E
—
T
–
is valid with V
MAX691A
MAX693A
RESET
CC
CC
down to GND.
15
rises above the reset threshold
CC
CC
must be below the reset
is below the reset thresh-
Watchdog Function
1kΩ
TO μP RESET
Watchdog Input
CC
falls below
The Watchdog Output (WDO) remains high if there is a
transition or pulse at WDI during the watchdog timeout
period. The watchdog function is disabled and
a logic high when V
tery-backup mode is enabled, or WDI is an open circuit.
In watchdog mode, if no transition occurs at WDI during
the watchdog timeout period, RESET and RESET are
asserted for the reset timeout period (200ms typical).
WDO goes low and remains low until the next transition
at WDI (Figure 2). If WDI is held high or low indefinitely,
RESET and RESET will generate 200ms pulses every
1.6s. WDO has a 2 x TTL output characteristic.
The OSC SEL and OSC IN inputs control the watchdog
and reset timeout periods. Floating OSC SEL and OSC
IN or tying them both to V
watchdog timeout period and 200ms reset timeout peri-
od. Connecting OSC IN to GND and floating or connect-
ing OSC SEL to V
watchdog timeout delay and 1.6s delay immediately
after reset. The reset timeout delay remains 200ms
(Figure 2). Select alternative timeout periods by con-
necting OSC SEL to GND and connecting a capacitor
between OSC IN and GND, or by externally driving OSC
IN (Table 1 and Figure 3). OSC IN is internally connect-
ed to a ±100nA (typ) current source that charges and
discharges the timing capacitor to create the oscillator
frequency, which sets the reset and watchdog timeout
periods (see Connecting a Timing Capacitor at OSC IN
in the Applications Information section).
Figure 2. Watchdog Timeout Period and Reset Active Time
WDI
WDO
RESET
t
t
t
1
2
3
= RESET TIMEOUT PERIOD
= NORMAL WATCHDOG TIMEOUT PERIOD
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY AFTER RESET
t
1
Watchdog and Reset Timeout Period
CC
t
OUT
2
is below the reset threshold, bat-
t
1
selects the 100ms normal
OUT
Selecting an Alternative
selects the nominal 1.6s
t
3
Watchdog Output
–
WDO is