X4043M8IZ-2.7A Intersil, X4043M8IZ-2.7A Datasheet

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X4043M8IZ-2.7A

Manufacturer Part Number
X4043M8IZ-2.7A
Description
IC CPU SUPERV 4K EEPROM 8-MSOP
Manufacturer
Intersil
Type
Simple Reset/Power-On Resetr
Datasheet

Specifications of X4043M8IZ-2.7A

Number Of Voltages Monitored
1
Output
Open Drain or Open Collector
Reset
Active Low
Reset Timeout
100 ms Minimum
Voltage - Threshold
2.92V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
CPU Supervisor with 4kbit EEPROM
FEATURES
• Selectable watchdog timer
• Low V
• Low power CMOS
• 4kbits of EEPROM
• Built-in inadvertent write protection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
—Five standard reset threshold voltages
—Adjust low V
—Reset signal valid to V
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
—16-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes
—8 Ld SOIC
—8 Ld MSOP
—8 Ld PDIP
special programming sequence
of EEPROM array with Block Lock
SDA
SCL
V
WP
CC
CC
detection and reset assertion
CC
reset threshold voltage using
V
CC
Reset logic
Command
Decode &
®
Register
Control
Threshold
Logic
Data
1
CC
Watchdog Transition
= 1V
Data Sheet
Detector
V
TRIP
protection
EEPROM Array
Protect Logic
1-888-INTERSIL or 1-888-468-3774
Register
+
Status
-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
DESCRIPTION
The X4043/45 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply
Voltage Supervision, and Block Lock Protect Serial
EEPROM Memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low V
user’s system from low voltage conditions, resetting the
system when V
point. RESET/RESET is asserted until V
proper operating level and stabilizes. Five industry stan-
dard V
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
Power-on and
Timer Reset
Low Voltage
Generation
Watchdog
Watchdog
Timebase
Reset &
March 16, 2006
TRIP
out
Reset
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
thresholds are available, however, Intersil’s
interval,
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
CC
falls below the minimum V
CC
detection circuitry protects the
the
X4043, X4045
device
4k, 512 x 8 Bit
RESET (X4043)
RESET (X4045)
activates
CC
FN8118.2
returns to
CC
the
trip

Related parts for X4043M8IZ-2.7A

X4043M8IZ-2.7A Summary of contents

Page 1

... V Generation TRIP CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. X4043, X4045 4k, 512 x 8 Bit FN8118.2 interval, the ...

Page 2

... X4043S8IZ-2.7A* (Note) X4043 Z AP X4045S8IZ-2.7A (Note) X4045 Z AP X4043M8-2.7A ADE X4045M8-2.7A X4043M8Z-2.7A (Note) DAY X4045M8Z-2.7A (Note) DBG X4043M8I-2.7A ADF X4045M8I-2.7A X4043M8IZ-2.7A (Note) DAT X4045M8IZ-2.7A (Note) DBC X4043P-2.7A X4043P AN X4045P-2.7A X4043PZ-2.7A (Note) X4043P Z AN X4045PZ-2.7A (Note) X4043PI-2.7A X4043P AP X4045PI-2.7A X4043PIZ-2.7A (Note) X4043P Z AP X4045PIZ-2.7A (Note) ...

Page 3

... X4043 G X4045S8I-2.7 X4043S8IZ-2.7 (Note) X4043 Z G X4045S8IZ-2.7 (Note) X4043M8-2.7 ADG X4045M8-2.7 X4043M8Z-2.7 (Note) DAX X4045M8Z-2.7 (Note) X4043M8I-2.7 ADH X4045M8I-2.7 X4043M8IZ-2.7(Note) DAS X4045M8IZ-2.7 (Note) X4043P-2.7 X4043P F X4045P-2.7 X4043PZ-2.7 (Note) X4043P Z F X4045PZ-2.7 (Note) X4043PI-2.7 X4043P G X4045PI-2.7 X4043PIZ-2.7 (Note) X4043P Z G X4045PIZ-2.7 (Note) *Add " ...

Page 4

... EEPROM array with Intersil’s block lock protection. The array is internally organized The device features an 2-wire interface and software protocol 2 allowing operation bus. The device utilizes Intersil’s proprietary Direct Write cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. Pin (SOIC/MSOP/DIP) Name ...

Page 5

PRINCIPLES OF OPERATION Power-on Reset Application of power to the X4043/45 activates a Power-on Reset Circuit that pulls the RESET/RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. ...

Page 6

Setting a V Voltage TRIP There are two procedures used to set the threshold voltages (V ), depending if the threshold voltage to TRIP be stored is higher or lower than the present value. For example, if the present V ...

Page 7

Figure 3. Reset V Level Sequence (V TRIP SCL SDA A0h Figure 4. Sample V Reset Circuit TRIP 4.7K RESET V TRIP Adj. 7 X4043, X4045 > 3V 15-18V, ...

Page 8

Figure 5. V Programming Sequence TRIP New V applied = CC Old V applied + | Error | CC Error < MDE Control Register The control register provides the user a mechanism for changing the block lock and watchdog timer ...

Page 9

The state of the control register can be read at any time by performing a random read at address 1FFh, using the special preamble. Only one byte is read by each register read operation. The X4043/45 resets itself after the ...

Page 10

SERIAL INTERFACE Serial Interface Conventions The device supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer ...

Page 11

Figure 8. Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver Start X4043/45 ADDRESSING Slave Address Byte Following a start condition, the master must output a slave address byte. This byte consists of several ...

Page 12

Figure 10. Byte Write Sequence Signals from the Master SDA Bus Signals from the Slave Page Write The device is capable of a page write operation initiated in the same manner as the byte write opera- tion; but ...

Page 13

Acknowledge Polling The disabling of the inputs during nonvolatile cycles can be used to take advantage of the typical 5kHz write cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the ...

Page 14

Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the slave address byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The ...

Page 15

Data Protection The following circuitry has been included to prevent inadvertent writes: – The WEL bit must be set to allow write operations. – The proper clock count and bit sequence is required prior to the stop bit in order ...

Page 16

ABSOLUTE MAXIMUM RATINGS Temperature under bias ................... -65°C to +135°C Storage temperature ........................ -65°C to +150°C Voltage on any pin with respect to V ...................................... -1.0V to +7V SS D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds) ........ ...

Page 17

CAPACITANCE (T = 25° 1.0 MHz Symbol (4) C Output capacitance (SDA, RESET/RESET) OUT (4) C Input capacitance (SCL, WP) IN Notes: (4) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT ...

Page 18

TIMING DIAGRAMS Bus Timing t F SCL t SU:STA t HD:STA SDA IN SDA OUT WP Pin Timing START SCL SDA IN t SU:WP WP Write Cycle Timing SCL th SDA 8 Bit of Last Byte Nonvolatile Write Cycle Timing ...

Page 19

Power-Up and Power-Down Timing V TRIP Volts t R RESET (X4043) RESET (X4045) RESET Output Timing Symbol V Reset trip point voltage, X4043/45-4.5A TRIP Reset trip point voltage, X4043/45 Reset trip point voltage, X4043/45-2.7A Reset trip point ...

Page 20

Watchdog Time Out For 2-Wire Interface Start SCL SDA (4043) RESET Minimum Sequence to Reset WDT SCL SDA V Set/Reset Conditions TRIP (V TRIP t TSU WP t VPS SCL 0 SDA A0h Start 20 X4043, X4045 Start Clockin (0 ...

Page 21

V Programming Specifications: V TRIP Parameter t WP Program Voltage Setup time VPS t WP Program Voltage Hold time VPH t V Level Setup time TSU TRIP t V Level Hold (stable) time THD TRIP t V Program Cycle WC ...

Page 22

PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S Pin 1 Index 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 22 X4043, X4045 Pin ...

Page 23

PACKAGING INFORMATION 8-Lead Miniature Small Outline Gull Wing Package Type M 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.036 (0.91) 0.032 (0.81) 0.040 ± 0.002 (1.02 ± 0.05) 0.007 (0.18) 0.005 (0.13) 23 X4043, X4045 0.118 ± ...

Page 24

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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