TLE4473G V53 Infineon Technologies, TLE4473G V53 Datasheet - Page 5

• Manufacturer Part Number: TLE4473G V53
• Description: IC REGULATOR LDO DUAL PDSO-12-6
• Manufacturer: Infineon Technologies

Specifications of TLE4473G V53

• Regulator Topology: Positive Fixed
• Voltage - Output: 3.3V, 5V
• Voltage - Input: 5.6 ~ 42 V
• Voltage - Dropout (typical): -, 0.3V @ 100mA
• Number Of Regulators: 2
• Current - Output: 300mA (Max), 180mA (Max)
• Current - Limit (min): 350mA, 200mA
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: DSO-12
• Number Of Outputs: 2
• Polarity: Positive
• Input Voltage Max: 42 V
• Output Voltage: 3.3 V, 5 V
• Output Type: Fixed
• Dropout Voltage (max): 0.6 V at 100 mA
• Output Current: 300 mA, 180 mA
• Line Regulation: 20 mV
• Load Regulation: 50 mV
• Voltage Regulation Accuracy: 3 %
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Packages: PG-DSO-12
• Regulator Type: multiple output
• Accuracy: 3.0 %2.0 %
• Max. Output Current: 300mA180mA
• Dropout Voltage: 300mV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SP000014118; SP000557254; TLE4473G V53; TLE4473G V53TR; TLE4473GV53NT; TLE4473GV53T

Figure 3
Table 1
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
Heatsink
Data Sheet
Symbol Function
WI
RO2
RO1
Q2
Q1
N.C.
I
INH1
INH2
D2
D1
GND
N. C.
Pin Configuration TLE 4473 GV53, TLE 4473 GV52 (top view)
Pin Definitions and Functions (TLE 4473 GV53, TLE 4473 GV52)
Watchdog input; input for watchdog pulses, positive edge
triggered
Reset output for Q2; open collector output
Reset and watchdog output for Q1; open collector output
Output voltage 2 (5 V); block to GND with a capacitor
ESR < 5 Ω at 10 kHz or
Output voltage 1 (3.3 V/2.6 V); block to GND with a capacitor
C
Not connected; connect to GND
Input voltage; block to GND directly at the IC with a ceramic
capacitor.
Inhibit input 1; low level at INH2 and INH1 disables Q2 and Q1
Inhibit input 2; low level disables Q2
Reset Delay 2; connect a capacitor to set reset delay for Q2
Reset Delay 1; connect a capacitor to GND to set reset delay and
watchdog timing for Q1
Ground
Not connected; connect to GND
Q1
≥ 10 µF, ESR < 5 Ω at 10 kHz
RO2
RO1
N.C.
Q2
Q1
WI
1
2
3
4
5
6
P-DSO-12-6
5
C
AEP03318_4473gv53.VSD
Q2
≥ 10 µF, ESR < 4 Ω at 10 kHz
12
11
10
9
8
7
Pin 6 and heat slug should be connected to GND
GND
D1
D2
INH2
INH1
I
Rev. 1.0, 2004-07-14
TLE 4473 GV53
TLE 4473 GV52
C
Q2
≥ 22 µF,