MCP1725-5002E/SN Microchip Technology, MCP1725-5002E/SN Datasheet - Page 18

• Manufacturer Part Number: MCP1725-5002E/SN
• Description: IC LDO REG 500MA 5.0V 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP1725-5002E/SN

• Regulator Topology: Positive Fixed
• Voltage - Output: 5V
• Voltage - Input: Up to 6V
• Voltage - Dropout (typical): 0.21V @ 500mA
• Number Of Regulators: 1
• Current - Output: 500mA (Min)
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Primary Input Voltage: 5.35V
• Output Voltage: 5V
• Dropout Voltage Vdo: 210mV
• No. Of Pins: 8
• Output Current: 500mA
• Voltage Regulator Case Style: SOIC
• Operating Temperature Range: -40°C To +125°C
• Number Of Outputs: 1
• Polarity: Positive
• Input Voltage Max: 6 V
• Output Type: Fixed
• Dropout Voltage (max): 0.35 V at 500 mA
• Line Regulation: 0.05 % / V
• Load Regulation: 0.5 %
• Voltage Regulation Accuracy: 2 %
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Output Voltage Fixed: 5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP1725
4.6
The C
timing for the power good output, as discussed in the
previous section. By adding a capacitor from the
C
delay can be adjusted from 200 µs (no capacitance on
C
See Section 1.0 “Electrical Characteristics” for
C
Once the power good threshold (rising) has been
reached, the C
to V
PWRGD output will transition high when the C
voltage has charged to 0.42V. If the output falls below
the power good threshold limit during the charging time
between 0.0V and 0.42V on the C
C
ting the timer. The C
output voltage of the LDO has once again risen above
the power good rising threshold. A timing diagram
showing C
Figure
FIGURE 4-4:
Diagram.
DS22026B-page 18
DELAY
DELAY
DELAY
DELAY
V
0V
OUT
PWRGD
IN
DELAY
. The charging current is 140 nA (typical). The
4-4.
) to 300 ms (0.1 µF of capacitance on C
timing tolerances.
pin voltage will be pulled to ground, thus reset-
T
pin to ground, the PWRGD power-up time
C
PG
DELAY
DELAY
input is used to provide the power-up delay
C
DELAY
DELAY
, PWRGD and V
C
V
DELAY
PWRGD_TH
Input
DELAY
pin charges the external capacitor
C
Threshold (0.42V)
DELAY
pin will be held low until the
V
IN
(typ)
and PWRGD Timing
OUT
DELAY
is shown in
DELAY
pin, the
DELAY
pin
).
4.7
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN threshold is a
percentage of the input voltage. The typical value of
this shutdown threshold is 30% of V
and maximum limits over the entire operating
temperature range of 45% and 15%, respectively.
The SHDN input will ignore low-going pulses (pulses
meant to shut down the LDO) that are up to 400 ns in
pulse width. If the shutdown input is pulled low for more
than 400 ns, the LDO will enter Shutdown mode. This
small bit of filtering helps to reject any system noise
spikes on the shutdown input signal.
On the rising edge of the SHDN input, the shutdown
circuitry has a 30 µs delay before allowing the LDO
output to turn on. This delay helps to reject any false
turn-on signals or noise on the SHDN input signal. After
the 30 µs delay, the LDO output enters its soft-start
period as it rises from 0V to its final regulation value. If
the SHDN input signal is pulled low during the 30 µs
delay period, the timer will be reset and the delay time
will start over again on the next rising edge of the
SHDN input. The total time from the SHDN input going
high (turn-on) to the LDO output being in regulation is
typically 100 µs. See
the SHDN input.
FIGURE 4-5:
Diagram.
V
SHDN
OUT
30 µs
Shutdown Input (SHDN)
T
OR
70 µs
Figure 4-5
Shutdown Input Timing
© 2007 Microchip Technology Inc.
for a timing diagram of
IN
, with minimum
400 ns (typ)