MCP1725-5002E/SN Microchip Technology, MCP1725-5002E/SN Datasheet - Page 22

• Manufacturer Part Number: MCP1725-5002E/SN
• Description: IC LDO REG 500MA 5.0V 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP1725-5002E/SN

• Regulator Topology: Positive Fixed
• Voltage - Output: 5V
• Voltage - Input: Up to 6V
• Voltage - Dropout (typical): 0.21V @ 500mA
• Number Of Regulators: 1
• Current - Output: 500mA (Min)
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Primary Input Voltage: 5.35V
• Output Voltage: 5V
• Dropout Voltage Vdo: 210mV
• No. Of Pins: 8
• Output Current: 500mA
• Voltage Regulator Case Style: SOIC
• Operating Temperature Range: -40°C To +125°C
• Number Of Outputs: 1
• Polarity: Positive
• Input Voltage Max: 6 V
• Output Type: Fixed
• Dropout Voltage (max): 0.35 V at 500 mA
• Line Regulation: 0.05 % / V
• Load Regulation: 0.5 %
• Voltage Regulation Accuracy: 2 %
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Output Voltage Fixed: 5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP1725
5.3.2
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below:
As you can see from the result, this application will be
operating near around a junction temperature of
100°C. The PCB layout for this application is very
important as it has a significant impact on the junction-
to-ambient thermal resistance (Rθ
package, which is very important in this application.
5.3.3
From this table, you can see the difference in maximum
allowable power dissipation between the 2x3 DFN
package and the 8-pin SOIC package. This difference
is due to the exposed metal tab on the bottom of the
DFN package. The exposed tab of the DFN package
provides a very good thermal path from the die of the
LDO to the PCB. The PCB then acts like a heatsink,
providing more area to distribute the heat generated by
the LDO.
DS22026B-page 22
2x3 DFN (76°C/W Rθ
SOIC8 (163°C/Watt Rθ
P
P
P
P
D(MAX)
D(MAX)
D(MAX)
D(MAX)
T
T
T
JUNCTION TEMPERATURE
ESTIMATE
MAXIMUM PACKAGE POWER
DISSIPATION AT 60°C AMBIENT
TEMPERATURE
J
J
J
= T
= 38.8°C + 60.0°C
= 98.8°C
JRISE
=
=
=
=
(125°C – 60°C) / 76°C/W
0.855W
(125°C – 60°C)/ 163°C/W
0.399W
JA
+ T
JA
):
):
A(MAX)
JA
) of the 2x3 DFN
5.4
Where:
For a delay of 300ms,
C = 333.3E-09 *.300
C = 100E-09 µF (0.1 µF)
C
=
ΔT
ΔV
C
I
I
C
•
DELAY
------ -
Δ
Δ
V
T
=
=
=
=
=
(
--------------------------------- -
140nA
Calculations (typical)
C
C
140 nA typical.
time delay
C
typical
C
DELAY
DELAY
DELAY
0.42V
© 2007 Microchip Technology Inc.
=
•
I
Δ
•
threshold voltage, 0.42V
Capacitor
charging current,
T
ΔT
------ -
ΔV
)
=
333.3
×10
–
09
•
Δ
T