LP38692MPX-ADJ/NOPB National Semiconductor, LP38692MPX-ADJ/NOPB Datasheet - Page 13

• Manufacturer Part Number: LP38692MPX-ADJ/NOPB
• Description: IC REG LDO 1A ADJ SOT223-5
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LP38692MPX-ADJ/NOPB

• Regulator Topology: Positive Adjustable
• Voltage - Output: 1.25 ~ 9 V
• Voltage - Input: 2.7 ~ 10 V
• Voltage - Dropout (typical): 0.45V @ 1A
• Number Of Regulators: 1
• Current - Output: 1A
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SOT-223 (4 leads + Tab)
• For Use With: LP38692EVAL - BOARD EVALUATION LP38692
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -
• Other names: LP38692MPX-ADJ

If used in a dual-supply system where the regulator output
load is returned to a negative supply, the output pin must be
diode clamped to ground to limit the negative voltage transi-
tion. A Schottky diode is recommended for this protective
clamp.
PCB LAYOUT
Good PC layout practices must be used or instability can be
induced because of ground loops and voltage drops. The in-
put and output capacitors must be directly connected to the
input, output, and ground pins of the regulator using traces
which do not have other currents flowing in them (Kelvin con-
nect).
The best way to do this is to lay out C
device with short traces to the V
regulator ground pin should be connected to the external cir-
cuit ground so that the regulator and its capacitors have a
"single point ground".
It should be noted that stability problems have been seen in
applications where "vias" to an internal ground plane were
used at the ground points of the IC and the input and output
capacitors. This was caused by varying ground potentials at
these nodes resulting from current flowing through the ground
plane. Using a single point ground technique for the regulator
and it’s capacitors fixed the problem. Since high current flows
through the traces going into V
Kelvin connect the capacitor leads to these pins so there is
no voltage drop in series with the input and output capacitors.
LLP MOUNTING
The SDE06A (No Pullback) 6-Lead LLP package requires
specific mounting techniques which are detailed in National
Semiconductor Application Note # 1187. Referring to the sec-
tion PCB Design Recommendations in AN-1187 (Page 5),
it should be noted that the pad style which should be used
with the LLP package is the NSMD (non-solder mask defined)
type. Additionally, it is recommended the PCB terminal pads
to be 0.2 mm longer than the package pads to create a solder
fillet to improve reliability and inspection.
The input current is split between two V
two V
device can meet all specifications at the rated current.
The thermal dissipation of the LLP package is directly related
to the printed circuit board construction and the amount of
additional copper area connected to the DAP.
The DAP (exposed pad) on the bottom of the LLP package is
connected to the die substrate with a conductive die attach
adhesive. The DAP has no direct electrical (wire) connection
to any of the pins. There is a parasitic PN junction between
the die substrate and the device ground. As such, it is strongly
recommend that the DAP be connected directly to the ground
at device lead 2 (i.e. GND). Alternately, but not recommend-
ed, the DAP may be left floating (i.e. no electrical connection).
The DAP must not be connected to any potential other than
ground.
For the LP38690-ADJ and LP38692-ADJ in the SDE06A 6-
Lead LLP package, the junction-to-case thermal rating, θ
is 10.4°C/W, where the case is the bottom of the package at
the center of the DAP. The junction-to-ambient thermal per-
formance for the LP38690-ADJ and LP38692-ADJ in the
SDE06A 6-Lead LLP package, using the JEDEC JESD51
standards is summarized in the following table:
IN
pins must be connected together to ensure that the
IN
, V
IN
OUT
and coming from V
, and ground pins. The
IN
IN
and C
pins, 1 and 6. The
OUT
near the
OUT
JC
,
,
13
RFI/EMI SUSCEPTIBILITY
RFI (radio frequency interference) and EMI (electromagnetic
interference) can degrade any integrated circuit’s perfor-
mance because of the small dimensions of the geometries
inside the device. In applications where circuit sources are
present which generate signals with significant high frequen-
cy energy content (> 1 MHz), care must be taken to ensure
that this does not affect the IC regulator.
If RFI/EMI noise is present on the input side of the regulator
(such as applications where the input source comes from the
output of a switching regulator), good ceramic bypass capac-
itors must be used at the input pin of the IC.
If a load is connected to the IC output which switches at high
speed (such as a clock), the high-frequency current pulses
required by the load must be supplied by the capacitors on
the IC output. Since the bandwidth of the regulator loop is less
than 100 kHz, the control circuitry cannot respond to load
changes above that frequency. This means the effective out-
put impedance of the IC at frequencies above 100 kHz is
determined only by the output capacitor(s).
In applications where the load is switching at high speed, the
output of the IC may need RF isolation from the load. It is
recommended that some inductance be placed between the
output capacitor and the load, and good RF bypass capacitors
be placed directly across the load.
PCB layout is also critical in high noise environments, since
RFI/EMI is easily radiated directly into PC traces. Noisy cir-
cuitry should be isolated from "clean" circuits where possible,
and grounded through a separate path. At MHz frequencies,
ground planes begin to look inductive and RFI/ EMI can cause
ground bounce across the ground plane. In multi-layer PCB
applications, care should be taken in layout so that noisy
power and ground planes do not radiate directly into adjacent
layers which carry analog power and ground.
OUTPUT NOISE
Noise is specified in two ways- Spot Noise or Output
Noise density is the RMS sum of all noise sources, measured
at the regulator output, at a specific frequency (measured with
a 1Hz bandwidth). This type of noise is usually plotted on a
curve as a function of frequency. Total Output Noise or
Broad-Band Noise is the RMS sum of spot noise over a
specified bandwidth, usually several decades of frequencies.
Attention should be paid to the units of measurement. Spot
noise is measured in units µV/root-Hz or nV/root-Hz and total
output noise is measured in µV(rms)
The primary source of noise in low-dropout regulators is the
internal reference. Noise can be reduced in two ways: by in-
creasing the transistor area or by increasing the current drawn
by the internal reference. Increasing the area will decrease
the chance of fitting the die into a smaller package. Increasing
the current drawn by the internal reference increases the total
supply current (ground pin current).
JESD 51-3
JESD 51-7
2–Layer
4–Layer
JEDEC
JEDEC
Board
Type
Thermal
None
Vias
1
2
4
6
10.4°C/W
10.4°C/W
10.4°C/W
10.4°C/W
10.4°C/W
θ
JC
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237°C/W
74°C/W
60°C/W
49°C/W
45°C/W
θ
JA