MCR908JL3EMPE Freescale Semiconductor, MCR908JL3EMPE Datasheet - Page 60

• Manufacturer Part Number: MCR908JL3EMPE
• Description: IC MCU 4K FLASH 8MHZ 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCR908JL3EMPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 23
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

System Integration Module (SIM)
IF14 — Interrupt Flags
Bit 0 to 6 — Always read 0
5.5.2.3 Interrupt Status Register 3
IF15 — Interrupt Flags
Bit 1 to 7 — Always read 0
5.5.3 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
5.5.4 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting its
break interrupt output. (See
state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to
see how each module is affected by the break state.
5.5.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains
cleared even when break mode is exited. Status flags with a two-step clearing mechanism — for example,
a read of one register followed by the read or write of another — are protected, even when the first step
is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step
will clear the flag as normal.
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This flag indicates the presence of interrupt requests from the sources shown in
These flags indicate the presence of interrupt requests from the sources shown in
1 = Interrupt request present
0 = No interrupt request present
1 = Interrupt request present
0 = No interrupt request present
Address:
Reset:
Read:
Write:
$FE06
Bit 7
R
R
0
0
Figure 5-14. Interrupt Status Register 3 (INT3)
Chapter 15 Break Module
= Reserved
MC68HC908JL3E Family Data Sheet, Rev. 4
R
6
0
0
R
5
0
0
R
4
0
0
(BREAK).) The SIM puts the CPU into the break
R
3
0
0
R
2
0
0
R
1
0
0
Freescale Semiconductor
Table
Table
Bit 0
IF15
R
0
5-3.
5-3.