MCIMX31LVKN5 Freescale Semiconductor, MCIMX31LVKN5 Datasheet - Page 77

• Manufacturer Part Number: MCIMX31LVKN5
• Description: IC MPU MAP I.MX31L 457-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX31r

Specifications of MCIMX31LVKN5

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, ATA, EBI/EMI, FIR, I²C, MMC/SD, PCMCIA, SIM, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, POR, PWM, WDT
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.22 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 457-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

1
conditions may be device specific.
2
3
4
5
6
7
8
9
10
IP36 Controls hold time for write
IP37 Slave device data delay
IP38 Slave device data hold time
IP39 Write data setup time
IP40 Write data hold time
IP41 Read period
IP42 Write period
IP43 Read down time
IP44 Read up time
IP45 Write down time
IP46 Write up time
IP47 Read time point
Tdicuw
Tdicpw
Tdicdr
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These
Tdicur
Tdrp
Tdicpr
Tdicdw
Freescale Semiconductor
ID
Display interface clock period value for read:
Display interface clock period value for write:
Display interface clock down time for read:
Display interface clock up time for read:
Display interface clock down time for write:
Display interface clock up time for write:
This parameter is a requirement to the display connected to the IPU
Data read point
Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific.
=
=
=
=
=
T HSP_CLK ceil
=
=
1
-- - T
2
1
-- - T
2
T
1
-- - T
2
T
1
-- - T
2
HSP_CLK
HSP_CLK
HSP_CLK ceil
HSP_CLK ceil
HSP_CLK ceil
Table 50. Asynchronous Parallel Interface Timing Parameters—Access Level (continued)
HSP_CLK ceil
Parameter
⋅
⋅
⋅
⋅
3
ceil
⋅
2
ceil
⋅
5
7
⋅
------------------------------------------------- -
HSP_CLK_PERIOD
DISP#_READ_EN
9
6
DISP#_IF_CLK_PER_RD
--------------------------------------------------------------- -
4
DISP#_IF_CLK_PER_WR
----------------------------------------------------------------- -
2 DISP#_IF_CLK_DOWN_RD
-------------------------------------------------------------------------------
2 DISP#_IF_CLK_UP_RD
--------------------------------------------------------------------
2 DISP#_IF_CLK_UP_WR
--------------------------------------------------------------------- -
2 DISP#_IF_CLK_DOWN_WR
-------------------------------------------------------------------------------- -
HSP_CLK_PERIOD
⋅
⋅
HSP_CLK_PERIOD
⋅
⋅
HSP_CLK_PERIOD
HSP_CLK_PERIOD
HSP_CLK_PERIOD
HSP_CLK_PERIOD
8
8
Symbol
Tdicpw Tdicpw–1.5
Tdicdw Tdicdw–1.5
Tdicuw Tdicuw–1.5
Tdchw Tdicpw–Tdicdw–1.5
Tdicpr
Tdicdr
Tdicur
Tracc
Tdrp
Troh
Tds
Tdh
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
0
Tdrp–Tlbd–Tdicdr+1.5
Tdicdw–1.5
Tdicpw–Tdicdw–1.5
Tdicpr–1.5
Tdicdr–1.5
Tdicur–1.5
Tdrp–1.5
Min.
Tdicpw–Tdicdw
Tdicdw
Tdicpw–Tdicdw
Tdicpr
Tdicpw
Tdicdr
Tdicur
Tdicdw
Tdicuw
Tdrp
Typ.
—
—
1
Tdrp
Tdicpr–Tdicdr–1.5
Tdicpr+1.5
Tdicpw+1.5
Tdicdr+1.5
Tdicur+1.5
Tdicdw+1.5
Tdicuw+1.5
Tdrp+1.5
9
–Tlbd
Electrical Characteristics
Max.
10
—
—
—
–Tdicur–1.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
77