EVAL-ADF7012EB1 Analog Devices Inc, EVAL-ADF7012EB1 Datasheet
EVAL-ADF7012EB1
Specifications of EVAL-ADF7012EB1
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EVAL-ADF7012EB1 Summary of contents
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FEATURES Single-chip, low power UHF transmitter 75 MHz to 1 GHz frequency operation Multichannel operation using Frac-N PLL 2 3.6 V operation On-board regulator—stable performance Programmable output power: −16 dBm to +14 dBm, 0.4 dB steps Data rates: ...
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ADF7012 TABLE OF CONTENTS Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 6 Transistor Count........................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 315 MHz ........................................................................................ 8 433 MHz ........................................................................................ 9 868 MHz ...
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SPECIFICATIONS DV = 2.3 V – 3.6 V; AGND = DGND = Table 1. Parameter RF OUTPUT CHARACTERISTICS Operating Frequency Phase Frequency Detector MODULATION PARAMETERS Data Rate FSK/GFSK Data Rate ASK/OOK Deviation FSK/GFSK GFSK BT ASK ...
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ADF7012 Parameter PHASE-LOCKED LOOP PARAMETERS VCO Gain 315MHz 433MHz 868MHz 915MHz VCO Tuning Range Spurious (IVCO Min/Max) Charge Pump Current Setting [00] Setting [01] Setting [10] Setting [11] 1 Phase Noise (In band) 315MHz 433MHz 868MHz 915MHz 1 Phase Noise ...
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TIMING CHARACTERISTICS ± 10%; AGND = DGND = Table 2. Parameter Limit MIN MAX ...
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ADF7012 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter DV to GND DD (GND = AGND = DGND = 0 V) Digital I/O Voltage to GND Analog I/O Voltage to GND Operating Temperature Range Maximum ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Functional Descriptions Pin No. Mnemonic Description 1 DV Positive Supply for the Digital Circuitry. This must be between 2.3 V and 3.6 V. Decoupling capacitors to the analog DD ground plane should ...
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ADF7012 TYPICAL PERFORMANCE CHARACTERISTICS 315 MHZ –60 –70 –80 –90 –100 –110 –120 –130 –140 1.0k 10.0k 100.0k PHASE NOISE (Hz) Figure 4. Phase Noise Response—DV DD IVCO = 2.0 mA 315 MHz, PFD = 3.6864 MHZ, PA ...
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MHZ 1 2.00V/ 2 1.00V/ 1.50ms 500µs TRIG'D 2 CLKOUT 1 CE Figure 10. Crystal Power-On Time, 4 MHz, Time = 1.6 ms –40 FREQUENCY = 393.38 kHz –60 LEVEL = –102.34dBc/Hz –80 –100 –120 –140 –160 –180 –200 ...
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ADF7012 868 MHZ 0 FREQUENCY = 251.3 kHz –20 LEVEL = –99.39dBc/Hz –40 –60 –80 –100 –120 –140 –160 1.0k 10.0k 100.0k PHASE NOISE (Hz) Figure 16. Phase Noise Response–I = 2.5 mA MHz, PFD = 4.9152 MHz, ...
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MHZ –40 FREQUENCY = 992.38 kHz –60 LEVEL = –102.34dBc/Hz –80 –100 –120 –140 –160 –180 –200 1.0k 10.0k 100.0k PHASE NOISE (Hz) Figure 21. Phase Noise Response–I = 1.44 mA MHz, PFD =10 MHz, Power = ...
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ADF7012 CIRCUIT DESCRIPTION PLL OPERATION A fractional-N PLL allows multiple output frequencies to be generated from a single-reference oscillator (usually a crystal) simply by changing the programmable N value found in the N register. At the phase frequency detector (PFD), ...
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The output buffer to CLK is enabled by setting Bit DB4 in OUT the function register high. On power-up, this bit is set high. The output buffer can drive load with a 10% rise time ...
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ADF7012 PFD/ 4R CHARGE PUMP FSK DEVIATION FREQUENCY –F DEV THIRD-ORDER Σ-∆ MODULATOR +F DEV TxDATA FRACTIONAL-N Figure 30. The deviation from the center frequency is set using bits the modulation register. The frequency deviation may ...
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The nonlinear characteristic of the output stage results in an output spectrum containing harmonics of the fundamental, especially the third and fifth. To meet local regulations, a low- pass filter usually is required to filter these harmonics. The output stage ...
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ADF7012 OUTPUT DIVIDER An output divider is a programmable divider following the VCO in the PLL loop useful when using the ADF7012 to generate frequencies of < 500 MHz. REFERENCE LOOP PFD CP VCO DIVIDER FILTER ÷N Figure ...
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THEORY OF OPERATION CHOOSING THE EXTERNAL INDUCTOR VALUE The ADF7012 allows operation at many different frequencies by choosing the external VCO inductor to give the correct output frequency. Figure 36 shows both the minimum and maximum frequency vs. the inductor ...
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ADF7012 Setting Tuning Sensitivity Value The tuning sensitivity usually denoted in MHz/V and is required for the loop filter design. It refers to the amount that a change of a volt in the voltage applied to VCO ...
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APPLICATION EXAMPLES V DD C5+ V 10µF DD 2.2µF J1 TxDATA 1kΩ 1kΩ TxCLK 1kΩ MUXOUT 27pF 27pF J2 C9 1kΩ CLK OUT R3 CLK CLK 1kΩ J3–3 R4 DATA DATA 1kΩ J3–5 R5 1kΩ ...
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ADF7012 315 MHZ OPERATION The recommendations here are guidelines only. The design should be subject to internal testing prior to FCC site testing. Matching components need to be adjusted for board layout. The FCC standard 15.231 regulates operation in the ...
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MHZ OPERATION The recommendations here are guidelines only. The design should be subject to internal testing prior to ETSI site testing. Matching components need to be adjusted for board layout. The ETSI standard EN 300-220 governs operation in the ...
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ADF7012 868 MHZ OPERATION The recommendations here are guidelines only. The design should be subject to internal testing prior to ETSI site testing. Matching components need to be adjusted for board layout. The ETSI standard EN 300-220 governs operation in ...
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MHZ OPERATION The recommendations here are guidelines only. The design should be subject to internal testing prior to FCC site testing. Matching components need to be adjusted for board layout. FCC 15.247 and FCC 15.249 are the main regulations ...
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ADF7012 REGISTER DESCRIPTIONS R REGISTER OUTPUT VCO DIVIDER ADJUST OD2 OD1 OUTPUT DIVIDER 0 0 DISABLED 0 1 DIVIDE DIVIDE DIVIDE BY 8 VA2 VA1 VCO ADJUST VCO ADJUSTMENT ...
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N-COUNTER LATCH P1 PRESCALER 0 4/5 1 8/9 8-BIT INTEGER-N 12-BIT FRACTIONAL-N M12 M11 M10 ....... ....... ....... ....... ....... . . . . ...
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ADF7012 MODULATION REGISTER TEST BITS MUST BE LOW IC2 MC3 GFSK MOD MODULATION DEVIATION CONTROL IF AMPLITUDE SHIFT KEYING SELECTED, TxDATA = OFF 0 . ...
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FUNCTION REGISTER SD TEST PLL TEST MODES MODES PA3 PA2 PA1 PA BIAS 5µ 6µ 7µ 12µA VCO BIAS VB4 ...
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... Temperature Range ADF7012BRU −40°C to +85°C ADF7012BRU-REEL −40°C to +85°C ADF7012BRU-REEL7 −40°C to +85°C EVAL-ADF7012EB1 EVAL-ADF7012EB2 EVAL-ADF7012EB3 EVAL-ADF7012EB4 EVAL-ADF7012EB5 © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04617–0–10/04(0) 7 ...