EVAL-ADF7012EB1 Analog Devices Inc, EVAL-ADF7012EB1 Datasheet - Page 17

• Manufacturer Part Number: EVAL-ADF7012EB1
• Description: BOARD EVALUATION FOR EB1 ADF7012
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF7012EB1

• Module/board Type: Evaluation Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: ADF7020 928MHz
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant

THEORY OF OPERATION
CHOOSING THE EXTERNAL INDUCTOR VALUE
The ADF7012 allows operation at many different frequencies by
choosing the external VCO inductor to give the correct output
frequency. Figure 36 shows both the minimum and maximum
frequency vs. the inductor value. These are measurements based
on 0603 CS type inductors from Coilcraft, and are intended as
guidelines in choosing the inductor because board layout and
inductor type varies between applications.
The inductor value should be chosen so it is between the
minimum and maximum value.
For frequencies between 270 MHz and 550 MHz, it is
recommended to operate the VCO at twice the desired output
frequency and use the divide-by-2 option. This ensures reliable
operation over temperature and supply.
For frequencies between 130 MHz and 270 MHz, it is
recommended to operate the VCO at four times the desired
output frequency and use the divide-by-4 option.
For frequencies below 130 MHz, it is best to use the divide-by-8
option. It is not necessary to use the VCO divider for
frequencies above 550 MHz.
ADIsimPLL is a PLL design tool which can perform the
frequency calculations for the ADF7012, and is available at
www.analog.com/pll.
CHOOSING THE CRYSTAL/PFD VALUE
The choice of crystal value is an important one. The PFD
frequency must be the same as the crystal value or an integer
division of it. The PFD determines the phase noise, spurious
levels and location, deviation frequency, and the data rate in the
case of GFSK. The following sections describe some factors that
should be considered when choosing the crystal value.
1200
1100
1000
900
800
700
600
500
400
300
Figure 36. Output Frequency vs. External Inductor Value
0
5
10
Ibias = 2.0 mA.
INDUCTANCE (nH)
15
20
25
MIN (meas)
MAX (meas)
MIN (eqn)
MAX (eqn)
30
35
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Standard Crystal Values
Standard crystal values are 3.6864 MHz, 4 MHz, 4.096 MHz,
4.9152 MHz, 7.3728 MHz, 9.8304 MHz, 10 MHz, 11.0592 MHz,
12 MHz, and 14.4792 MHz. Crystals with these values are
usually available in stock and cost less than crystals with
nonstandard values.
Reference Spurious Levels
Reference spurious levels (spurs) occur at multiples of the PFD
frequency. The reference spur closest to the carrier is usually
highest with the spur further out being attenuated by the loop
filter. The level of reference spur is lower for lower PFD
frequencies. In designs with high output power where spurious
levels are the main concern, a lower PFD frequency (<5 MHz)
may be desirable.
Beat Note Spurs
These are spurs occurring for very small or very large values in
the fractional register. These are quickly attenuated by the loop
filter. Selection of the PFD therefore determines their location,
and ensures that they have negligible effect on the transmitter
spectrum.
Phase Noise
The phase noise of a frequency synthesizer improves by 3dB for
every doubling of the PFD frequency. Because ACP is related to
the phase noise, the PFD may be increased to reduce the ACP
in the system. PFD frequencies of < 5MHz typically deliver
sufficient phase noise performance for most systems.
Deviation Frequency
The deviation frequency is adjustable in steps of
To get the exact deviation frequency required, ensure F
factor of the desired deviation.
TIPS ON DESIGNING THE LOOP FILTER
The loop filter design is crucial in ensuring stable operation of
the transmitter, meeting Adjacent Channel Power (ACP)
specifications, and meeting spurious requirements for the
relevant regulations. ADIsimPLL is a free tool available to aid
the design of loop filters. The user enters the desired frequency
range, the reference crystal and PFD values, and the desired
loop bandwidth. ADIsimPLL gives a good starting point for the
filter, and the filter can be further optimized based on the
criteria below.
F
STEP
(
Hz
)
=
F
2
PFD
14
ADF7012
STEP
is a
(10)