T4260-IL Atmel, T4260-IL Datasheet
T4260-IL
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T4260-IL Summary of contents
Page 1
... Bus (Enable, Clock and Data and 5 V Microcontrollers- compatible) Description The T4260 is an advanced AM/FM receiver with integrated fast PLL as a single-chip solution based on Atmel’s high-performance BICMOS II technology. The low-imped- ance driver at the IF output is designed for the A digital IF. The fast tuning concept realized in this part is based on patents held by Atmel and allows lock times less than 1 ms for a jump over the FM band with a step width of 12 ...
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... VRT 38 GNDT 39 MXAMOB 40 MXAMOA 41 VST 42 RFAGCA1 43 MXFMOA 44 MXFMOB T4260 2 Function DAC1 output DAC2 output FM AGC current FM mixer input A FM mixer input B RF ground AM mixer input B AM mixer input A AM AGC current AM IF-AGC filter 2 Switch 2/AM AGC voltage RF AM-AGC filter 2 Switching output 1 ...
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... REFFREQ OSCGND The T4260 implements an AM up-conversion reception path from the RF input signal to the IF output signal. A VCO and an LO prescaler for AM are integrated to generate the LO frequency to the AM mixer. The FM reception path generates the same LO frequency from the RF input signal by a down-conversion to the IF output. The IF A/D output is designed for digital signal processing ...
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... Reference oscillator 2.3 input voltage 2.4 Reference frequency *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40°C to +85°C) but are tested at +25°C T4260 4 Symbol SPLL P ...
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... SATH 1 DAC1,2 0.3 V -0.6 DAC1,2 S 0.9 0.98 1.1 -0.9 -0.98 -1.1 2.06 2.09 2.13 0.63 0.67 0.73 60 170 60 140 150 150 OSC 75 163 133 3 2.6 3.1 3.6 T4260 Unit Type (1) µA A (1) µA A (1) µA A (1) µ (1) – A (1) – ...
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... RF-AGC AM threshold 11.4 (programmable with bit 12 - bit 15) *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40°C to +85°C) but are tested at +25°C T4260 +8 +25°C ST SPLL ...
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... T4260 Type* (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) ...
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... Hold time EN 17.8 Hold time DATA *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40°C to +85°C) but are tested at +25°C T4260 +8 +25°C ST SPLL ...
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... The register settings of the T4260 are programmed by a 3-wire bus protocol. The bus protocol consists of separate commands. A defined number of bits is transmitted sequentially during each command. One command is used to program all bits of one register. The different registers avail- able (see chapter “ ...
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... Figure 4. 3-wire Bus Timing Diagram t F Enable Data Clock T4260 HDA High V t Low HEN High V Low High V Low 4528J–AUDR–11/04 ...
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... MSB BYTE 3 ADDR (1) ( 101 100 LSB LSB High SW- SW- c.CP impulse wire HI/ ON/ ON/ LO OFF OFF LSB 1 = SW2 SW2 SW1 0 = AGC 1 = low 1 = low x 1/0 1/0 1 T4260 LSB Divider VCO 143 142 141 140 LSB N2 Divider (1) ( 121 120 119 118 LSB N1 Divider (1) ( ...
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... ADDR. AM/FM RF-AGC AGC 1/0 1 A8_01 MSB BYTE 1 ADDR. IF-IN VCO AM/FM HI/ A8_00 MSB BYTE 1 PLL PD TE/ ADDR. N2/N1 ON/ PD OFF ( 1/0 1 Note: 1. Value has T4260 12 LSB MSB ADDR LSB x HCDEL ( LSB LSB IF-Gain LSB IF-AGC BYTE 2 LSB SHIFT ( 1/0 ...
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... Table 4. PD-Test Mode PD TE/PD Pin 17 = AMLF output (standard) Pin Test mode The N2/N1 bit controls the active N-divider. Only one of the two N-Divider can be active. The N1-Divider is activated by setting bit the N2-Divider by setting bit Table 5. N-Divider N2/N1 N1-divider active N2-divider active B16 T4260 ...
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... IF Amplifier VCO RF-AGC T4260 14 The IF gain amplifier can be used in AM and FM mode to compensate the loss of the external ceramic bandfilters. The IF gain can be controlled in 2-dB steps by setting bit 6 to bit 9 as given in Table 6. Table 6. IF Gain IF Gain ... ... The selection of the IF amplifier input can be controlled by bit 11 as given in Table 7. ...
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... There are two registers, HCDEL 1 (bits 20 and 21) and HCDEL 2 (bits 22 and 23), to control the delay time of the high-current charge pump and to deactivate them. bit 18 (HCDEL) determines whether register HCDEL used. Table 12. High-current Charge Pump Delay Time Register HCDEL 1/2 Select Mode HCDEL 1 HCDEL 2 B15 B14 B13 ... ... ... B17 HCDEL (B18 T4260 B12 ... ...
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... Shift SW1 (Pin 13) T4260 16 If bits 20 and 21 (HCDEL 1) or bits 22 and 23 (HDCEL 2) are both set to 0, then the high-current charge pump is deactivated. Otherwise, the delay time can be selected as described in Table 13. Table 13. Delay Time of HCDEL Register High-current Charge Pump OFF Delay time 5 ns ...
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... The AM mixer is used for up-conversion of the AM reception frequency to the IF frequency. Therefore prescaler is implemented to generate the necessary LO frequency from the VCO frequency. The VCO divider can be controlled by the bits 140 to 143 as given in Table 18 on page 18. (The VCO divider is only active in AM mode) T4260 B48 B47 0 X ...
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... FM Mixer PLL Loop Filter Fractional Mode T4260 18 Table 18. Divider Factor of the AM Prescaler Divider AM Prescaler Divide by 2 Divide by 3 Divide by 4 Divide by 5 Divide by 6 Divide by 7 Divide by 8 Divide by 9 Divide the FM mixer stage, the FM reception frequency is down-converted to the IF frequency. The VCO frequency is used as LO frequency for the mixer. ...
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... At the AMLF (pin 17), an external tuning voltage can be applied (bit 65 = 0). If this is not done, the IC operates in standard mode (bit 65 = 1). The oscillator, oscillator buffer and the AMLF are controlled by the bits 65 and 64 as given in Table 25 on page 20. T4260 B60 0 1 ...
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... DAC1, 2 (Pins 1, 2) T4260 20 Table 25. Oscillator Operating Modes Oscillator Oscillator Buffer OFF INPUT ON OFF ON OUTPUT For automatic tuner alignment, the DAC1 and DAC2 of the IC can be controlled by set- ting gain and offset values. The principle of the operation is shown in Figure 7. The gain is in the range of 0. ...
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... It is also possible to reduce the gain or the offset value instead of (or along with) the tun- ing voltage and the offset gain given in Table 27. B28 B26 B26 B25 B24 B56 B55 B54 B53 B52 ... ... ... ... ... ... ... ... ... ... T4260 Decimal Offset Decimal Offset ... 64 ... 125 126 127 21 ...
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... Input/Output Interface Circuits VTUNE, AMLF and FMLF (Pins 16-18) EN, DATA, CLK (Pins 23-25) T4260 22 Figure 8. Internal Components of DAC1, 2 DAC1, 2 VTUNE is the loop amplifier output of the PLL. The bipolar output stage is a rail-to-rail amplifier. Figure 9. Internal Components at VTUNE, AMLF and FMLF V S VTUNE All functions can be controlled via a 3-wire bus consisting of Enable, Data and Clock ...
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... The output signals of the 18-bit N-divider and 14-bit R-divider will be compared in the PHASEDETECTOR which one activates the sink and source currents of the charge pumps (CP). BIT 18 BIT 32 B145 AM - LOOP AM/FM FILTER FM - LOOP AM/FM PUMP FILTER FILTER VCO B62,63 B61 T4260 23 ...
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... High-speed Tuning T4260 24 There are also two HCDEL registers (for the high current CP delay time) but only one of them is active. One of the HCDEL registers can be activated by bit 18. The delay time of the HCDEL register can be selected with bit 20 and bit 21 or bit 22 and bit 23). The current for the high CP (HCCP) can be set by bit 62 and the current for the low current CP (LCCP) by bit 63 ...
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... V to VSPLL - 1 V for a good S/N performance. Minimum Reception Maximum Reception Frequency [MHz] Frequency [MHz] 87.5 38.4 22.033 13.85 8.94 5.667 3.329 1.575 0.211 0 from 98.2 MHz to 124 MHz is only an exam- VCO T4260 113.3 51.3 30.633 20.3 14.1 9.967 7.014 4.8 3.078 1.7 25 ...
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... By using two ICs, for example possible to operate the AMLF (pin 17) of the second IC either with the tuning voltage (VTUNE [pin 18]), the DAC 1 voltage [pin 1] or the DAC 2 voltage [pin 2] from the first T4260. For voltage reduction at the AMLF [pin 17], a voltage factor ratio of 100/16 (R ...
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... VRVCO IFAGCFM 100n 15 VSPLL IFOUTA 16 FMLF IFOUTB 17 AMLF GNDPLL 18 VTUNE REFFREQ 19 OSCGND VRPLL 1n 20 OSCE DATA 22p 47p 21 OSCB CLK 22 OSCBUF EN 10n 10n Test Point 44 330 100n VST 100n 36 330 35 2k4 34 100n 33 100k 32 100k 31 30 100 10n 10n 25 24 BUS 23 T4260 27 ...
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... Figure 14. Application Circuit R 5 5R6 R VST 5R6 100n 10µ DAC1 10n 16 DAC2 10n 68k 470 R 10 10p 2µ2 18 10n BFR93A Bu1 Ant T4260 180 1µ 100n 2k2 300 F1 6 300 220n 100n 47p 100p 100n 100n C 31 12p L 2 100µH C ...
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... Ordering Information Extended Type Number T4260-ILSH T4260-ILQH Package Information Package SSO44 Dimensions in mm 0.3 0 4528J–AUDR–11/04 Package Remarks Pb-free SSO44 Tube Pb-free SSO44 Taped and reeled 18.05 17.80 0.25 0.10 16 9.15 8.65 7.50 7.30 2.35 10.50 10.20 technical drawings according to DIN ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...