T4260-IL Atmel, T4260-IL Datasheet - Page 24

• Manufacturer Part Number: T4260-IL
• Description: IC RECEIVER AM/FM FRONT 44-SSOP
• Manufacturer: Atmel

Specifications of T4260-IL

• Frequency: AM, FM
• Modulation Or Protocol: AM, FM
• Applications: AM/FM Radio Receiver
• Current - Receiving: 85mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 8 V ~ 10 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -

High-speed Tuning
24
T4260
There are also two HCDEL registers (for the high current CP delay time) but only one of
them is active. One of the HCDEL registers can be activated by bit 18. The delay time of
the HCDEL register can be selected with bit 20 and bit 21 or bit 22 and bit 23). The
current for the high CP (HCCP) can be set by bit 62 and the current for the low current
CP (LCCP) by bit 63.
With bit 145 the AM- or FM-Loopfilter (pin) can be activated. It is also possible to use the
AM-Loopfilter in FM mode (instead of the FM-Loopfilter) or the FM-Loopfilter in AM
mode.
The fractional mode (bit 144 = 0) in connection with the direct shift mode (bit 32 = 0)
a l l o w s v e r y f a s t f r e q u e n c y c h a n g e s w i t h f o u r t i m e s t h e s t e p f r e q u e n c y
(50 kHz = 4
the R- and the N-divider are shifted by 2 bits to the right (this corresponds to a R- and
N-divider division by 4 or a step frequency multiplication by 4).
Due to the 2-bit shift, a faster tuning response time of approximately 1 ms instead of
3-4 ms for a tune over the whole FM band from 87.5 MHz to 108 MHz is possible with
f
If the FM receiving frequency is 103.2125 MHz (with e.g. f
f
reference-frequency (f
An important condition for the use of the fractional mode is an R-divider with an integer
value after the division by 4 (R-dividers have to be a multiple of 4).
After a 2-bit shift (divider division by 4), the R-divider is now 3 (instead of 12) and the
N-divider is 2278.25 (instead of 9113). The new N-divider of 2278.25 is also called ¼
fractional step because the modulo value of the N-divider is 0.25 = ¼. In total, there are
4 different fractional 2-bit shift steps: full, ¼, ½ and ¾ step.
If the fractional mode is switched off (bit 144 = 1) during direct shift mode (bit 32 = 0), the
modulo value of the N-divider will be ignored (the new N-divider is then 2278 instead of
2278.25). This means that the PLL locks on the next lower multiple frequency of
4
(instead of 113.9125 MHz in fractional mode).
Also the PLL has additionally a special fractional logic which allows a good spurious
suppression in the fractional and direct shift mode. Activating the wire switch (bit 60 = 1)
and the correction charge pump (bit 60 = 1) the spurious suppression is active.
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IF
= 10.7 MHz), an N-divider of 9113 and an R-divider of 12 are necessary when using a
= 12.5 kHz.
f
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f
f
VCO
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(in our case f
= f
= f
VCO
IF
f
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+ f
/N = f
rec
) at low frequency steps (e.g., f
= 10.7 MHz + 103.2125 MHz = 113.9125 MHz
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ref
ref
/R = 113.9125 MHz/9113 = 150 kHz/12 = 12.5 kHz
) of 150 kHz.
= 12.5 kHz). The new VCO frequency (f
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= 12.5 kHz). In direct shift mode,
VCO
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) is then 113.9 MHz
= 12.5 kHz and
4528J–AUDR–11/04