ATA5824-PLQW Atmel, ATA5824-PLQW Datasheet - Page 55

• Manufacturer Part Number: ATA5824-PLQW
• Description: IC TXRX UHF ASK/FSK 48QFN
• Manufacturer: Atmel

Specifications of ATA5824-PLQW

• Frequency: 433 ~ 435MHz; 866 ~ 870MHz
• Data Rate - Maximum: 20kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Power - Output: 10dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.15 V ~ 3.6 V or 4.4 V ~ 5.25 V
• Current - Receiving: 10.5mA
• Current - Transmitting: 10.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

14.1.4
14.1.5
Figure 14-2. Timing Diagram for Complete Successful Bit-check
4829D–RKE–06/06
(Number of checked bits: 3)
Bit-check Mode
Bit-check Configuration
RX_ACTIVE
Demod_Out
Bit check
Start-up mode
T
Startup_Sig_Proc
In Bit-check mode the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter and signals due to noise. This is done by subsequent time
frame checks where the distance between 2 signal edges are continuously compared to a pro-
grammable time window. The maximum count of this edge to edge test before the transceiver
switches to receiving mode is also programmable.
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks are verify-
ing one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The
maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N
control register 5. This implies 0, 6, 12 and 18 edge to edge checks respectively. If N
set to a higher value, the transceiver is less likely to switch to receiving mode due to noise. In the
presence of a valid transmitter signal, the Bit-check takes less time if N
value. In RX polling mode, the Bit-check time is not dependent on N
present.
According to
its. If the edge to edge time t
Bit-check limit T
T
Figure 14-3. Valid Time Window for Bit-check
Lim_max
, the Bit-check will be terminated and the transceiver switches to sleep mode.
Figure 14-2
Figure
1/2 Bit
Demod_Out
Lim_max
14-3, the time window for the Bit-check is defined by two separate time lim-
shows an example where 3 bits are tested successful.
, the check will be continued. If t
1/2 Bit
ee
Bit check mode
T
is in between the lower Bit-check limit T
1/2 Bit
Bit-check
Bit check ok
T
T
Lim_max
Lim_min
1/2 Bit
t
ee
1/2 Bit
1/f
ee
Signal
is smaller than limit T
ATA5823/ATA5824
1/2 Bit
Bit-check
Receiving mode
Bit-check
Lim_min
if no valid signal is
Lim_min
is set to a lower
and the upper
or exceeds
Bit-check
Bit-check
55
in
is