SI4421-A0-FT Silicon Laboratories Inc, SI4421-A0-FT Datasheet - Page 13

• Manufacturer Part Number: SI4421-A0-FT
• Description: IC TXRX FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4421-A0-FT

• Frequency: 433MHz, 868MHz, 915MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK
• Applications: ISM
• Power - Output: 7dbm
• Sensitivity: -110dBm
• Voltage - Supply: 2.2 V ~ 3.8 V
• Current - Receiving: 15mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1737-5

CONTROL INTERFACE
Commands to the transmitter are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on
pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands
consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-
bit command). Bits having no influence (don’t care) are indicated with X. Special care must be taken when the microcontroller’s built-
in hardware serial port is used. If the port cannot be switched to 16-bit mode then a separate I/O line should be used to control the
nSEL pin to ensure the low level during the whole duration of the command or a software serial control interface should be
implemented. The Power-On Reset (POR) circuit sets default values in all control and command registers.
The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events:
FFIT and FFOV are applicable when the RX FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To
identify the source of the IT, the status bits should be read out.
Timing Specification
Timing Diagram
SDO
nSEL
SCK
SDI
Symbol
 The TX register is ready to receive the next byte (RGIT)
 The RX FIFO has received the preprogrammed amount of bits (FFIT)
 Power-on reset (POR)
 RX FIFO overflow (FFOV) / TX register underrun (RGUR)
 Wake-up timer timeout (WKUP)
 Negative pulse on the interrupt input pin nINT (EXT)
 Supply voltage below the preprogrammed value is detected (LBD)
t
t
t
t
t
t
t
t
SHI
CH
DH
OD
CL
SS
SH
DS
t
SS
t
DS
BIT 15
FFIT
t
CH
t
DH
Parameter
Clock high time
Clock low time
Select setup time (nSEL falling edge to SCK rising edge)
Select hold time (SCK falling edge to nSEL rising edge)
Select high time
Data setup time (SDI transition to SCK rising edge)
Data hold time (SCK rising edge to SDI transition)
Data delay time
t
CL
FFOV
BIT 14
BIT 13
CRL
BIT 8
t
O D
AT S
BIT 7
OFFS(0)
BIT 1
FIFO OUT
BIT 0
t
Minimum value [ns]
SH
t
SHI
25
25
10
10
25
10
5
5
Si4421
13