SI4421-A0-FT Silicon Laboratories Inc, SI4421-A0-FT Datasheet - Page 25

• Manufacturer Part Number: SI4421-A0-FT
• Description: IC TXRX FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4421-A0-FT

• Frequency: 433MHz, 868MHz, 915MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK
• Applications: ISM
• Power - Output: 7dbm
• Sensitivity: -110dBm
• Voltage - Supply: 2.2 V ~ 3.8 V
• Current - Receiving: 15mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1737-5

14. Wake-Up Timer Command
The wake-up time period can be calculated by (m7 to m0) and (r4 to r0):
T
Note:
15. Low Duty-Cycle Command
With this command, autonomous low duty-cycle operation can be set in order to decrease the average power consumption in receive
mode.
Bits 7-1 (d6-d0):
Bit 0 (en): Enables the low duty-cycle Mode. Wake-up timer interrupt is not generated in this mode.
Note: In this operation mode, bit er must be cleared and bit ew must be set in the Power Management Command (page 15).
In low duty-cycle mode the receiver periodically wakes up for a short period of time and checks if there is a valid FSK transmission in
progress. FSK transmission is detected in the frequency range determined by Frequency Setting Command (page 17) plus and
minus the baseband filter bandwidth determined by the Receiver Control Command (page 17). This on-time is automatically
extended while DQD indicates good received signal condition.
When calculating the on-time take into account:
Choosing too short on-time can prevent the crystal oscillator from starting or the DQD signal will not go high even when the received
signal has good quality.
There is an application proposal on page 26. The Si4421 is configured to work in FIFO mode. The chip periodically wakes up and
switches to receiving mode. If valid FSK data received, the chip sends an interrupt to the microcontroller and continues filling the RX
FIFO. After the transmission is over and the FIFO is read out completely and all other interrupts are cleared, the chip goes back to low
power consumption mode.
wake-up
Bit
Bit
-
-
 For continual operation, the ew bit should be cleared and set at the end of every cycle.
 For future compatibility, use R in a range of 0 and 29.
= 1.03 · M · 2
15
15
1
1
the crystal oscillator, the synthesizer and the PLL needs time to start, see the AC Characteristics (Turn-on/Turnaround
timings) on page 11
depending on the DQD parameter, the chip needs to receive a few valid data bits before the DQD signal indicates good
signal condition (Data Filter Command, page 19)
14
14
1
1
The duty-cycle can be calculated by using (d6 to d0) and M. (M is parameter in a Wake-Up Timer Command, see
above). The time cycle is determined by the Wake-Up Timer Command.
duty-cycle= (D · 2 +1) / M · 100%
R
13
13
0
1
+ 0.5 [ms]
12
12
r4
0
11
11
r3
1
10
10
r2
0
r1
9
0
9
r0
8
0
8
m7
d6
7
7
m6
d5
6
6
m5
d4
5
5
m4
d3
4
4
m3
d2
3
3
m2
d1
2
2
m1
d0
1
1
m0
en
0
0
C80Eh
E196h
POR
POR
Si4421
25