TDA5150 Infineon Technologies, TDA5150 Datasheet
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TDA 5150 ...
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... Infineon Technologies Office. Infineon Technologies Components may be used in life-support devices or systems only with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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TDA 5150 Revision History: Previous Version: New issue We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this ...
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Table of Contents Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Digital FSK/GFSK Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.7.1 SFRs ...
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Product Description 1.1 Overview The TDA 5150 is a low cost and easy to implement, multi-channel ASK/FSK/GFSK RF transmitter for the 300-320 MHz, 425-450 MHz, 863 - 928 MHz frequency bands with low power consumption and RF-output power of ...
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... Minimum component count application circuit The TDA 5150 application circuit shown demonstrates the ease and simplicity of an intelligent transmitter implementation. The µC configures the TDA5150 via 3-wire SPI, the SDIO line is used at the same time to transfer data on SPI bus and as digital data input into the RF modulator. The CLKOUT line may be used as clock source for the µ ...
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The matching shown is an example for a loop antenna application. Different antenna types (electrical monopole or dipole, magnetic loop etc.) as well as different layout versions might require component values which can differ from those given in above example. ...
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Reduction of Spurs and Occupied Bandwidth The direct FSK modulation and in addition the Gaussian FSK (GFSK) reduces spurs and occupied bandwidth. Bandwidth reduction is exemplified below Figure 2 Spectrum of RF-signals with equal frequency deviations (+ 35kHz), same ...
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Integrated Data Encoder TDA 5150 comprises a Data Encoder which automatically generates encoded data from a regular (NRZ) bitstream. The supported data encoding modes are: • Manchester code • Differential Manchester code • Bi-phase space code • Bi-phase mark ...
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TESEUS - Configuration and Evaluation Tool Figure 3 TESEUS - First Tab of User Interface screen TESEUS is a user-friendly, comfortable tool, suitable for generation of TDA 5150 configurations and testing them using a TDA 5150 Evaluation Board. Configurations ...
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TDA 5150 Functional Description 2.1 PIN Configuration, Pin-out 2.2 Pin Definition and Pin Functionality Pin Name Pin No. Type 1 EN Digital Input 2 XTAL Analog Input Data Sheet XTAL 2 9 TDA 5150 GND 3 ...
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Pin Name Pin No. Type 3 GND Supply 4 VREG Analog Output 5 VBAT Supply Data Sheet Equivalent I/O Schematic XGND GND GNDD Triple bond GNDA VBAT GNDD VREG VREG Double bond GNDD VDDA GNDA VBAT VREG 13 TDA 5150 ...
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Pin Name Pin No. Type 6 PAOUT RF-PA Output 7 GNDPA Analog GND Data Sheet Equivalent I/O Schematic 10 PAOUT GNDPA GNDPA 14 TDA 5150 TDA 5150 Functional Description Function RF Power Amplifier Output (open drain) GNDPA RF Power Amplifier ...
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Pin Name Pin No. Type 8 CLKOUT Digital Output Data Sheet Equivalent I/O Schematic VBat 1.9 ... 3.6V VBat CLKOUT 500 GNDD GNDD GNDD 15 TDA 5150 Functional Description Function Programmable Divided Clock Data Enable Data Core VBat 0 1 ...
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Pin Name Pin No. Type 9 SCK Digital Input 10 SDIO Digital Input/ Output Data Sheet Equivalent I/O Schematic VBat SCK 250k GNDD GNDD VBat 1.9 ... 3.6V VBat 500 SDIO_DATA 250k GNDD GNDD GNDD 16 TDA 5150 Functional Description ...
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... ASK, FSK or GFSK) and encoding scheme. TDA 5150 contains following major blocks which extend the functionality compared to legacy RF transmitters: • An on-chip voltage regulator is delivering 2.1 V nominal supply voltage for the transmitter’s functional units. In addition, the battery voltage is monitored and battery low and brown out flags are set critical supply voltage drop event occurs. • ...
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... Special Function Registers TDA 5150 is configurable by programming the Special Function Register bank (abbreviated SFRs) via the SPI interface. Terminology and notations related to TDA5150 SFR set, list of symbols and programming restrictions are given in Detailed description of SFR map, programming, usage and content explanations are found in the following chapters (§ ...
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In STANDBY state, a special, low-power voltage regulator is activated, which is supplying only the SPI bus interface, the SFR registers and the system controller. In order to further reduce the current consumption, and keeping in mind that leakage currents ...
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Brownout is indicated by bit BROUTERR Note: The BOD itself can not be used to guarantee the correct operation of analog sections, where the minimum operating voltage is defined this is larger than the maximum ...
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SFRs related to Supply Voltage monitoring ADDR 0x01 TXSTAT—Transmitter Status Register Bit 7 Bit 6 Bit 5 1 n.u. LBD_2V1 / / Bit 7 1 Bit 5 LBD_2V1 Bit 4 LBD_2V4 Bit 3 reserved Bit 2 BROUTERR Bit 1 ...
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If SCK is at low level SCK while EN goes high, the incoming SDIO data is sampled by falling edge of the SCK and the output SDIO data is set by ...
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SCK SDIO Figure 7 SPI Timing — SCK high at rising edge of EN 2.4.3.2 SPI XOR Checksum The SPI block includes a safety feature for checksum calculation. This is achieved by means of XOR operation between ...
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Command Byte Structure First byte of each SPI sequence is the Command Byte, with the following structure: Function Code The first 2 bits C1 the Command Byte are the function code field. They ...
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Transmit Command The Transmit Command Byte is used for data transmission. It precedes the datagram to be transmitted. The Transmit Command Byte format is described in the following table Bit ...
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Timing Diagrams In the following timing diagrams the 4 possible SPI commands are shown. The examples are valid for the case of SCK is low when EN line goes from Low into High (rising edge). Therefore the incoming SDIO ...
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Note: In order to minimize cross-talk between SDIO and SCK lines recommended to keep the SCK either Low or High, but avoid transitions during RF transmission. Previous Chapter 2.4.3.4 Transmit Command Command structure. Data Sheet TDA 5150 Functional ...
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Data Encoder The Data Encoder is used in the so-called Synchronous Transmission Mode. A description of this transmission mode is found in Transmission. In Synchronous Transmission Mode the Encoder has to be used specific encoding of SDIO ...
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The Data Encoder option is enabled by bit C of Transmit Command (Data Encoder enabled if bit C=1). See also structure. If the Data Encoder is enabled, bit A must to be set for Synchronous Transmission Mode as well (Bit ...
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The feedback branches within the PRBS9 generator are fixed (as shown above), but the PRBS generation can be influenced by SFR configuration in the following manner: • A start value for the PRBS9 Generator can be programmed in SFR PRBS ...
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SFRs related to Transmitter Configuration and Data Encoding ADDR 0x05 TXCFG1—Transmitter Configuration Register 1 Bit 7 Bit 6 Bit 5 GO2SLEEP ASKFSK2 ASKFSK1 cw/0 w/0 w/1 Bit 3 INVERT Bit <2:0> ENCMODE INVERT Encoded data inversion enable 0: data ...
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ADDR 0x27 ENCCNT - Encoding start bit counter Bit 7 Bit 6 Bit 5 ENCCNT ENCCNT ENCCNT w/0 w/0 w/0 Bit <7:0> ENCCNT ENCCNT Sets the number of bits on start of a telegram which shall be sent unencoded or ...
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PLL division factor = (RF carrier frequency) / (crystal frequency) gives a fractional part (the part behind the decimal point) between 0.1 and 0.9. For example a ...
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If SDIO = 1 when EN goes High, the output clock is selected as imposed by settings of SFR CLKOUTCFG (0x06). This is the configurator register for Clock pre- and afterscaler. Detailed description of the bit-fields is given in ...
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SFRs related to Crystal Oscillator and Clock Divide r ADDR 0x06 CLKOUTCFG - Clock Pre- and Post-scaler Bit 7 Bit 6 Bit 5 CLKSRC CLKSRC AFTERSCAlE AFTERSCALE w/0 w/0 w/0 Bit <7:6> CLKSRC Bit <5:4> AFTERSCALE Bit <3:1> PRESCALE ...
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This RF signal is then further divided in a multimodulus divider block down to a frequency which is in same range as those of the reference signal’s, input from the reference oscillator (i.e the crystal oscillator). The reference oscillator’s frequency ...
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... Loop Filter Bandwidth In order to provide a high grade of flexibility by choice of modulation parameters, a PLL with programable bandwidth have been implemented in the TDA5150. The damping resistor(s), part of the active Loop Filter in PLL can be selected by means bit control field designated PLLBWTRIM in the SFR register PLLBW (0x25.6:4). ...
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PLL Dividers, RF Carrier Frequency The divider chain contains a fixed divider by 2 (prescaler), a band select divider, dividing by 1 for the 915 and 868 MHz bands for the 434 MHz band, and by 3 ...
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ADDR 0x09, 0x0D, PLLINTn—PLL MM Integer Value Channel 0x11, 0x15 n: Channel Bit 7 Bit 6 Bit 5 n.u. PLLINTn PLLINTn / w/1 w/0 Bit <6:0> PLLINTn PLLINTn Multi-modulus divider integer offset ...
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ADDR 0x0C, 0x10, PLLFRACn2—PLL Fractional Division Ratio 0x14, 0x18 n: Channel (byte 2) Bit 7 Bit 6 Bit 5 n.u. n.u. reserved / / w/0 Bit 5 reserved Bit <4:0> PLLFRACn2 PLLFRACn2 Synthesizer channel frequency value ...
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The GFSK modulation can further reduce the occupied RF bandwidth versus FSK modulation. The ASK or FSK modulation type is selected by a bit-field in SFR TXCFG1 (0x05). There are two possible setups, denoted ModulationSetting1, and ModulationSetting2. A field within ...
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The Gaussian shaping is defined as a number of fixed frequency steps (transitions) between the 2 FSK frequencies, corresponding to Low and High and 1 on the modulator input understood that the steps are counted over ...
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SFRs related to digital FSK / GFSK Modulator ADDR 0x1C FDEV—Frequency Deviation Bit 7 Bit 6 Bit 5 FDEVSCALE FDEVSCALE FDEVSCALE w/1 w/1 w/0 Bit <7:5> FDEVSCALE Bit <4:0> FDEV FDEVSCALE Scaling of the frequency deviation (3 bits) 000: ...
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ADDR 0x1E GFXOSC—Gaussian Filter Configuration Bit 7 Bit 6 Bit 5 FHBLANK reserved reserved w/0 w/1 w/1 Bit 7 FHBLANK Bit 3 GFBYP Bit <2:0> GFDIV FHBLANK Frequency Hopping disable (defines the jump from the TX_TIMEOUT state) 0: enable (jump ...
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Power Amplifier, ASK Modulator The RF signal, generated by VCO and under the control of the N PLL is fed to a group of class-C Power Amplifier stages, before being transmitted. The Power Amplifier (PA) includes an output power ...
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SLOPDIV from SDPLL Figure 17 PA Core with Output Power Control Two independent PA power level settings can be configured. With the Transmit Command the PA power level is selected together with the modulation setting. This means, either power ...
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The output impedance of the PA depends on the number of PA stages used. The external antenna matching must be done for the impedance related to the highest number of used PA stages other words, for the use-case ...
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The Duty Cycle Control is accessible through the bits DCCCONF ANTTDCC (0x1F).See Chapter DCCCONF In the 315 MHz band the DCCCONF and DCCDISABLE bits are ignored and the optimized (and predefined) value of 33% Duty Cycle is superimposed 2.4.8.4 Antenna ...
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... Fail-Safe mechanism is coupled with deactivation (switching off) of the RF Power Amplifier stages. If critical errors occur, the Fail-Safe mechanism incorporated in the TDA5150 is activated, provided the detection enable bit is armed (i.e. bit FSOFF in SFR TXCFG0 Observe that this corresponds to the after-reset state. In other words, by exiting the reset state, the Fail-Safe detection is already armed, but it can be deactivated anytime by changing its control bit state to High (bit FSOFF=1 (0x04 ...
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SFRs related to RF Power Amplifier and ASK Modulator ADDR 0x04 TXCFG0—Transmitter Configuration Register 0 Bit 7 Bit 6 Bit 5 GO2STDBY reserved reserved cw/0 w/0 w/0 Bit 4 FSOFF ADDR 0x05 TXCFG1—Transmitter Configuration Register 1 Bit 7 Bit ...
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ADDR 0x1A POWCFG0—PA Output Power Configuration Register 0 Bit 7 Bit 6 Bit 5 PA_PS2 PA_PS2 PA_PS2 w/0 w/0 w/0 Bit <7:5> PA_PS2 Bit <4:2> PA_PS1 Bit <1:0> SLOPEDIV PA_PS2 Individual control of the 3 PA blocks, setting 2 (3-bits) ...
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ADDR 0x1F ANTTDCC—Antenna Tuning and Duty Cycle Configurations Bit 7 Bit 6 Bit 5 reserved DCC DCCCONF DISABLE w/0 w/0 w/1 Bit 7 reserved Bit 6 DCCDISABLE Bit <5:4> DCCCONF Bit 3:0 TUNETOP DCCDISABLE Duty cycle control disable (must be ...
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Observe that this last wakeup condition is automatically fulfilled during communication over the transmitter’s SPI-bus, assuming a standard, SPI-bus protocol is used. SLEEP mode is entered: • after a GO2SLEEP command execution, i.e by taking the EN pin to Low ...
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TRANSMIT Mode This mode is automatically entered during a transmit command. PLL and PA are active i this mode. TRANSMIT is left, with the falling edge of the EN line, when bit B in the Transmit Command is 0. ...
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Power-On-Reset [ & [Activity on SCK ] ( clock pulses ) SLEEP = SLEEP Figure 19 Simplified State Diagram of the TDA 5150 Data Sheet TDA 5150 Functional Description Transmit command XOSC_ENABLE EN = ...
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SFRs related to Operating Modes ADDR 0x04 TXCFG0—Transmitter Configuration Register 0 Bit 7 Bit 6 Bit 5 GO2STDBY reserved reserved cw/0 w/0 w/0 Bit 7 GO2STDBY ADDR 0x05 TXCFG1—Transmitter Configuration Register 1 Bit 7 Bit 6 Bit 5 GO2SLEEP ...
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Fail-Safe Mechanism and Status Register 2.4.10.1 Fail-Safe Flags The status of the TDA 5150 is continuously monitored during active state. The integrated Fail-Safe mechanism includes: • Brownout Error—generates an internal reset, whenever the voltage drops below the specific threshold. ...
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SFRs related to Supply Voltage monitoring ADDR 0x01 TXSTAT—Transmitter Status Register Bit 7 Bit 6 Bit 5 1 n.u. LBD_2V1 / / Bit 7 1 Bit 5 LBD_2V1 Bit 4 LBD_2V4 Bit 3 reserved Bit 2 BROUTERR Bit 1 ...
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RF Data Transmission The procedure of RF Transmission starts by rising the EN line (pin 1) high. STANDBY or SLEEP Mode are exited, and the crystal oscillator started. The crystal oscillator requires maximum start up. During ...
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the PA is switched off by the falling edge of the EN line the SDIO line is latched with the falling edge of EN, the PA stays active, continuing to transmit according to the ...
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Asynchronous Transmission In Asynchronous Transmission Mode (also referred as Transparent Mode), the data on SDIO is directly input into modulator and converted into RF carrier.There is no internal synchronization with the bit-rate clock.The CLKOUT programmed to the proper bit-rate ...
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Synchronous Transmission In the Synchronous Transmission Mode the transmit data is latched with the falling edge of the internal bit clock, and thus synchronized. The bit clock at the CLKOUT has to be used by the µC to time ...
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Channel Hopping TDA 5150 offers the possibility for usage preconfigured RF channels, called and D frequency channels. The preconfiguration assumes proper programming PLL’s Multi-Modulus Integer Value registers A/B/C/D PLL Fractional Division Ratio ...
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Digital Control (SFR Registers) 2.5.1 SFR Register List The SFRs (Special Function Registers) are used to configure TDA 5150 and to read out certain information e.g. the transmitter status. There are complete SFRs, as well as register bits in ...
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PLLFRACD1 PLL fractional division ratio Channel D (byte 1) PLLFRACD2 PLL fractional division ratio Channel D (byte 2) SLOPEDIV ASK sloping clock divider low POWCFG0 PA output power configuration register 0 POWCFG1 PA output power configuration register 1 FDEV Frequency ...
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Register address Register address Register-bit position Register-bit position Register-bit command Register-bit command and reset value and reset value Figure 22 Register Terminology Register-bit command terminology read register r write register w clear-after-write c register Important notice mandatory to ...
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Table 4 Register Bit Map Configuration Register Addr Bit 7 SPICHKSUM 0x00 SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM TXSTAT 0x01 1 TXCFG0 0x04 GO2STDBY reserved TXCFG1 0x05 GO2SLEEP ASKFSK2 CLKOUTCFG 0x06 CLKSRC CLKSRC BDRDIV 0x07 BDRDIV BDRDIV PRBS ...
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SFR Detailed Descriptions ADDR 0x00 SPICHKSUM—SPI Checksum Register Bit 7 Bit 6 Bit 5 SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM c/0 c/0 c/0 Bit <7:0> SPICHKSUM SPICHKSUM Readout and clear the SPI checksum (8-bits), generated by each ...
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ADDR 0x04 TXCFG0—Transmitter Configuration Register 0 Bit 7 Bit 6 Bit 5 GO2STDBY reserved reserved cw/0 w/0 w/0 Bit 7 GO2STDBY Bit 6 reserved Bit 5 reserved Bit 4 FSOFF Bit <3:2> ISMB Bit 1 reserved Bit 0 reserved GO2STDBY ...
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ADDR 0x05 TXCFG1—Transmitter Configuration Register 1 Bit 7 Bit 6 Bit 5 GO2SLEEP ASKFSK2 ASKFSK1 cw/0 w/0 w/1 Bit 7 GO2SLEEP Bit <6:5> ASKFSK2:1 Bit 4 ASKSLOPE Bit 3 INVERT Bit <2:0> ENCMODE GO2SLEEP Set the chip into SLEEP mode ...
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ADDR 0x06 CLKOUTCFG - Clock Pre- and Post-scaler Bit 7 Bit 6 Bit 5 CLKSRC CLKSRC AFTERSCALE AFTERSCALE w/0 w/0 w/0 Bit <7:6> CLKSRC Bit <5:4> AFTERSCALE Bit <3:1> PRESCALE Bit 0 CLKOUTENA CLKSRC Clock output selection (2-bits) 00: prescaler ...
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ADDR 0x07 BDRDIV—Bit-rate Divider Bit 7 Bit 6 Bit 5 BDRDIV BDRDIV BDRDIV w/1 w/0 w/0 Bit <7:0> BDRDIV BRDRDIV Along with the pre-scaler and the post-scaler, Bit-rate clock divider value (8 bits), defines the data bit-rate, according to following ...
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ADDR 0x09 PLLINTA—PLL MM Integer Value Channel A Bit 7 Bit 6 Bit 5 n.u. PLLINTA PLLINTA / w/1 w/0 Bit <6:0> PLLINTA PLLINTA Multi-modulus divider integer offset value (7 bits) for Channel A ADDR 0x0A PLLFRACA0—PLL Fractional Division Ratio ...
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ADDR 0x0C PLLFRACA2—PLL Fractional Division Ratio Channel A (byte 2) Bit 7 Bit 6 Bit 5 n.u. n.u. reserved / / w/0 Bit 5 reserved Bit <4:0> PLLFRACA2 PLLFRACA2 Synthesizer channel frequency value (21 bits, bits < 20:16 >), fractional ...
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ADDR 0x0F PLLFRACB1—PLL Fractional Division Ratio Channel B (byte 1) Bit 7 Bit 6 Bit 5 PLLFRACB1 PLLFRACB1 PLLFRACB1 PLLFRACB1 PLLFRACB1 PLLFRACB1 PLLFRACB1 PLLFRACB1 w/0 w/0 w/0 Bit <7:0> PLLFRACB1 PLLFRACB1 Synthesizer channel frequency value (21 bits, bits < 15:8 ...
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ADDR 0x12 PLLFRACC0—PLL Fractional Division Ratio Channel C (byte 0) Bit 7 Bit 6 Bit 5 PLLFRACC0 PLLFRACC0 PLLFRACC0 PLLFRACC0 PLLFRACC0 PLLFRACC0 PLLFRACC0 PLLFRACC0 w/0 w/0 w/0 Bit <7:0> PLLFRACC0 PLLFRACC0 Synthesizer channel frequency value (21 bits, bits < 7:0 ...
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ADDR 0x14 PLLFRACC2—PLL Fractional Division Ratio Channel C (byte 2) Bit 7 Bit 6 Bit 5 n.u. n.u. reserved / / w/0 Bit 5 reserved Bit <4:0> PLLFRACC2 PLLFRACC2 Synthesizer channel frequency value (21 bits, bits < 20:16 >), fractional ...
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ADDR 0x17 PLLFRACD1—PLL Fractional Division Ratio Channel D (byte 1) Bit 7 Bit 6 Bit 5 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD1 w/0 w/0 w/0 Bit <7:0> PLLFRACD1 PLLFRACD1 Synthesizer channel frequency value (21 bits, bits < 15:8 ...
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ADDR 0x19 SLOPEDIV —ASK Sloping Clock Divider Bit 7 Bit 6 Bit 5 SLOPEDIV SLOPEDIV SLOPEDIV w/1 w/0 w/0 Bit <7:0> SLOPEDIV SLOPEDIV ASK sloping clock division ratio (10 bits, bits < 7:0 >), defines the slope of the ASK ...
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ADDR 0x1B POWCFG1—PA Output Power Configuration Register 1 Bit 7 Bit 6 Bit 5 POUT2 POUT2 POUT2 w/0 w/0 w/0 Bit <7:4> POUT2 Bit <3:0> POUT1 POUT2 PA output power setting 2 (4 bits), defines the number of enabled PA ...
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ADDR 0x1C FDEV—Frequency Deviation Bit 7 Bit 6 Bit 5 FDEVSCALE FDEVSCALE FDEVSCALE w/1 w/1 w/0 Bit <7:5> FDEVSCALE Bit <4:0> FDEV FDEVSCALE Scaling of the frequency deviation (3 bits) 000: divide by 64 100: divide by 4 FDEV Frequency ...
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ADDR 0x1D GFDIV—Gaussian Filter Divider Value Bit 7 Bit 6 Bit 5 GFDIV GFDIV GFDIV w/0 w/0 w/0 Bit <7:0> GFDIV GFDIV Gaussian filter clock divider value (11 bits, bits < 7:0 >), defines the sampling ratio of the Gaussian ...
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ADDR 0x1E GFXOSC—Gaussian Filter Configuration Bit 7 Bit 6 Bit 5 FHBLANK reserved reserved w/0 w/1 w/1 Bit 7 FHBLANK Bit <6:4> reserved Bit 3 GFBYP Bit <2:0> GFDIV FHBLANK Frequency Hopping, enable/disable VCO Auto Calibration for Channel Hopping 0: ...
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ADDR 0x1F ANTTDCC—Antenna Tuning and Duty Cycle Configurations Bit 7 Bit 6 Bit 5 reserved DCC DCCCONF DISABLE w/0 w/0 w/1 Bit 7 reserved Bit 6 DCCDISABLE Bit <5:4> DCCCONF Bit 3:0 TUNETOP DCCDISABLE Duty cycle control disable (must be ...
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ADDR 0x21 VAC0—VAC Configuration 0 Bit 7 Bit 6 Bit 5 VAC_CTR VAC_CTR VAC_CTR w/1 w/1 w/0 Bit <7:0> VAC_CTR VAC_CTR VCO autocalibration FAST counter (~100 MHz) compare value (9 bits, bits< 7:0 >) ADDR 0x22 VAC1—VAC Configuration 1 ...
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ADDR 0x24 CPCFG—Charge Pump Configurations Bit 7 Bit 6 Bit 5 n.u. reserved reserved / w/0 w/1 Bit <6:4> reserved Bit <3:0> CPTRIM CPTRIM Charge pump current trimming (4-bits): Range: Note: CPTRIM bits must be set correlated with PLLBW bits, ...
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ADDR 0x26 RES3—Reserved Bit 7 Bit 6 Bit 5 reserved reserved reserved w/1 w/1 w/0 Bit <7:0> reserved . ADDR 0x27 ENCCNT - Encoding start bit counter Bit 7 Bit 6 Bit 5 ENCCNT ENCCNT ENCCNT w/0 w/0 w/0 ...
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Applications 3.1 Simple application schematics example μC clocked by TDA 5150 SPI bus controlled by μC VBAT SDIO SCK μC EN XTAL / TIM / IRQ GND 8.2 pF 13.00 MHz EN XTAL GND VREG VBAT Figure 23 Simple ...
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Infineon Evaluation Board V1.1 GND Figure 24 Infineon Evaluation Board schematics (E.B. V1.1 board version) Data Sheet In Match GND GND JP2 GND GND 89 TDA 5150 Applications + JP1 V 1.0, July 2009 ...
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Figure 25 Component placement on Infineon Evaluation Board (V1.1, top side) Data Sheet 90 TDA 5150 Applications V 1.0, July 2009 ...
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Figure 26 Infineon Evaluation Board V1.1 top side, copper layer Data Sheet 91 TDA 5150 Applications V 1.0, July 2009 ...
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Figure 27 Infineon Evaluation Board V1.1 top side, solder mask Data Sheet 92 TDA 5150 Applications V 1.0, July 2009 ...
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Figure 28 Infineon Evaluation Board V1.1 bottom side, copper layer Data Sheet 93 TDA 5150 Applications V 1.0, July 2009 ...
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Figure 29 Infineon Evaluation Board V1.1 bottom side, solder mask Data Sheet 94 TDA 5150 Applications V 1.0, July 2009 ...
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Figure 30 Infineon Evaluation Board V1.1 drill map and tool list Data Sheet 95 TDA 5150 Applications V 1.0, July 2009 ...
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... TDA5150 see Table 6 see Table 6 see Table 6 see Table 6 see Table 6 see Table 6 see Table 6 Table 5 Bill of Materials, Infineon Evaluation Board V1.1 Note: frequency dependent component values (PA matching network for instance) are listed in Table 6 Table 6 Frequency band dependent component values Data Sheet ...
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Electrical Characteristics 4.1 Absolute Maximum Ratings Attention: Stresses above the maximum values listed below may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; ...
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Parameter A9 Maximum Input Voltage @ digital input pins A10 Maximum Current into digital input and output pins A11 Maximum Input Voltage @ XTAL pin (pin 2) Note1 not allowed to apply higher voltages than specified by A9, ...
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... See kHz Chapter 2.4.7 for frequency shift calculation ■ Total max. cap. MHz (including parasitics) between XTAL (pin2) and GND max Ohm 1)f = 13,56 MHz crystal °C amb ms with crystal NDK NX5032SA TDA5150 Evaluation Board V 1.0, July 2009 o C, unless on ...
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Pin # Parameter Symbol C10 CLKOUT f Output Frequency C11 Voltage V Regulator Output Voltage C12 Supply Current I Sleep Mode C13 Supply Current I Standby Mode C14 Low-Battery V Detector V Threshold C15 Brownout V Detector Voltage V Threshold ...
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Pin # Parameter Symbol C19 Supply Current I Transmit Mode I @868/915 MHz I C20 Power Level P Tolerance vs. P nominal value C21 Power Level P Variation vs. P temperature P C22 Power Level P ...
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Pin # Parameter Symbol C25 Band Switching t Time C26 Channel t Switching Time C27 SSB Phase Noise @ 315/434 MHz PLLBW = 150 kHz C28 SSB Phase Noise @ 868/915MHz PLLBW = 150 kHz Data Sheet Limit Values min ...
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SPI Characteristics Attention: Test ■ means that the parameter is not subject to production test. It was verified by design and/or characterization. SPI Timing Characteristics Table 10 Parameter Symbol D1 Clock f c Frequency D2 Clock High Time t ...
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Parameter Symbol D14 Input Data Tristate Setup t IDZSu Time D15 Output Data t NODZ Disable Time Table 11 SPI Electrical Characteristics Parameter Symbol E1 Input Low V Voltage E2 Input High V Voltage E3 Output Low V Voltage E4 ...
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Package Outline 0.5 A 0.22 0. 0.05 Marking 10 6 Notes All dimensions are Does not include plastic or metal protrusion of max . 0.15 mm per side 2) Does ...
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... Published by Infineon Technologies AG ...