ATA5279P-PLQW Atmel, ATA5279P-PLQW Datasheet - Page 5

• Manufacturer Part Number: ATA5279P-PLQW
• Description: IC ANTENNA DVR SIX-FOLD 48QFN
• Manufacturer: Atmel

Specifications of ATA5279P-PLQW

• Rf Type: PEG, TPMS
• Frequency: 125kHz
• Features: RSSI Equipped
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.2
9125L–RKE–03/11
Coil Driver Stage
The driver stage for each coil consists of two N-channel DMOS transistors. The low-side tran-
sistor is in Darlington configuration to maintain a source-follower characteristic.
Figure 3-1.
In the graphic above, the names of internal pins have a grey shaded background, and the
hatched area is not part of the driver stage itself but only used in diagnostic mode (please refer
to the Diagnosis Block description for further information on this topic).
The driver stages are supplied by the three VDS pins, which are tied together inside the chip.
A quiescence current regulation ensures low cross current while in idle state. The output tran-
sistors are monitored for current and temperature to protect them from damage caused by
irregular load conditions or too high ambient temperatures.
The driving stage is optimized for signal quality to ensure low harmonic distortions.
Two groups of driver stages are integrated: the first group is intended for high-current coils,
whereas the second group drives low-current coils. Note that there are certain coil impedance
ranges for each driver group. If the connected load exceeds this range, proper current regula-
tion and/or data modulation is not guaranteed.
While in idle mode and especially during a transmission, the driver stages of the five inactive
(i.e., not selected) coils are switched to high-side outputs, i.e., the positive coil connection
lines are tied to the VDS potential. The same applies to the return line inputs AxN. These mea-
sures ensure minimum parasitic currents in the disabled coils while the selected coil is
operating.
VSin_pre
Principle Driver Stage Setup
Internal nodes
GND
VDS
N
P
I
mirr1
I
mirr
HS
LS
P
mirr2
I
LS
N
pwr
Atmel ATA5279
Diag Enable
Diag Enable
I
I
HSDiag
LSDiag
Ax_State
AxP
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