XRT94L31IB-L Exar Corporation, XRT94L31IB-L Datasheet - Page 50

• Manufacturer Part Number: XRT94L31IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
A10
TXHDLCDAT_7_0
STS1TXA_D7_0
TXSBDATA_7_0
SIGNAL NAME
TXAISEN_0
I/O
I
TTL
TYPE
Transmit STS-1 Telecom Bus Interface - Channel 0 - Input Data Bus pin
number 7/Transmit High-Speed HDLC Controller Input Interface block -
Input Data Bus - Pin 7/Transmit DS3/E3 AIS Input Pin - Channel 0:
The function of this pin depends upon whether or not the STS-1 Tele-
com Bus Interface, associated with Channel 0 is enabled.
If STS-1 Telecom Bus (Channel 0) has been enabled -Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 7:
STS1TXA_0_D7:
This input pin along with STS1TXA_0_D[6:0] function as the Transmit
(Add) STS-1 Telecom Bus Interface - Input Data Bus for Channel 0. The
Transmit STS-1 Telecom Bus interface will sample and latch this pin
upon the falling edge of STS1TXA_CLK_0.
N
If the STS-1 Telecom Bus (associated with Channel 0) has been dis-
abled:
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in,
as described below.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed
HDLC Controller Input Interface block - Data Bus Input Pin # 7 -
Channel 0 - TXHDLCDAT_0_7:
If the XRT94L31 is configured to operate in the High-Speed HDLC Con-
troller over DS3/STS-3 Mode, then this input pin will function as Bit 5
within the Transmit High-Speed HDLC Controller Input Interface block -
Input Data Bus (e.g., the TxHDLCDat_0[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_0). The
Transmit High-Speed HDLC Controller Input Interface block will sample
the data residing on this input pin (along with the rest of the
TxHDLCDat_0[7:0] input pins) upon the rising edge of the TxHDLCClk_0
clock output signal.
If the XRT94L31 is configured to operate in any other mode that
involves the DS3/E3 Framer block - Transmit DS3/E3 AIS Enable
Input - Channel 0 - TXAISEN_0:
This input pin is used to command the Frame Generator block (within
Channel 0) to generate and transmit the DS3/E3 AIS pattern, as
described below.
•
•
N
OTE
OTE
"Low" - Configures the Frame Generator block to NOT generate and
transmit the DS3/E3 AIS Pattern
"High" - Configures the Frame Generator block to generate and
transmit the DS3/E3 AIS Pattern
: This input pin functions as the MSB (Most Significant Bit) of the
: If the user intends to control the transmission of DS3/E3 AIS via
Transmit (Add) Telecom Bus, for Channel 0.
Software, then this input pin mudt be tied to GND.
50
DESCRIPTION
REV. 1.0.1