XRT94L31IB-L Exar Corporation, XRT94L31IB-L Datasheet - Page 59

• Manufacturer Part Number: XRT94L31IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
AE15
TXHDLCDAT_2_0
STS1TXA_2_D0
SIGNAL NAME
TXGFCMSB_2
I/O
I/O
TTL/
CMOS
TYPE
Transmit STS-1 Telecom Bus Interface - Channel 2 - Input Data Bus
pin number 0/Transmit High-Speed HDLC Controller Input Interface
block - Channel 2 - Input Data Bus - Pin 0:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 2 is enabled.
If STS-1 Telecom Bus (Channel 2) has been enabled - Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 0 -
STS1TXA_2_D0:
This input pin along with STS1TXA_D_2[7:1] functions as the Transmit
(Add) STS-1 Telecom Bus Interface - Input Data Bus for Channel 2. This
particular input pin functions as the LSB (Least Significant Bit) input pin
on the Transmit (Add) STS-1 Telecom Bus Interface - Input Data Bus.
The Transmit STS-1 Telecom Bus interface will sample and latch this pin
upon the falling edge of STS1TXA_CLK_2.
The LSB of any byte, which is being input into the STS-1 Transmit Tele-
com Bus Interface - Data Bus (for Channel 2) should be input via this
pin.
If the STS-1 Telecom Bus (associated with Channel 2) has been dis-
abled:
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in,
as described below.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed
HDLC Controller Input Interface Block - Data Bus Input pin # 0 -
Channel 2 - TXHDLCDAT_2_0:
In this mode, this input pin will function as Bit 0 (the LSB) within the
Transmit High-Speed HDLC Controller Input Interface block - Input Data
Bus (e.g., the TxHDLCDat_2[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_2). The
Transmit High-Speed HDLC Controller Input Interface block will sample
the data residing on this input pin (along with the rest of the
TxHDLCDat_2[7:0] input pins) upon the rising edge of the TxHDLCClk_2
clock output signal.
TXGFCMSB_2 (Transmit GFC MSB Indicator - Channel 2)
This input pin will only function in this role if the XRT94L31 has been
configured to operate in the ATM UNI Mode.
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
59
DESCRIPTION
XRT94L31