MCP4461T-104E/ST Microchip Technology, MCP4461T-104E/ST Datasheet - Page 15

• Manufacturer Part Number: MCP4461T-104E/ST
• Description: IC DGTL POT 257TAPS 100K 20TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP4461T-104E/ST

• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Temperature Coefficient: 150 ppm/°C Typical
• Taps: 257
• Resistance (ohms): 100K
• Number Of Circuits: 4
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Pots: Quad
• Taps Per Pot: 257
• Resistance: 100 KOhms
• Wiper Memory: Non Volatile
• Buffered Wiper: Buffered
• Digital Interface: I2C
• Operating Supply Voltage: 2.7 V to 5.5 V
• Supply Current: 600 uA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Description/function: Quad I2C Digital POT with Nonvolatile Memory
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 1-3:
© 2010 Microchip Technology Inc.
I
Note 1:
2
102A
102B
103A
103B
Param.
C AC Characteristics
No.
106
2:
3:
4:
5:
6:
7:
(5)
(5)
(5)
(5)
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I
requirement t
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line
T
the SCL line is released.
The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between V
and V
must be tested in order to ensure that the output data will meet the setup and hold specifications for the
receiving device.
Use Cb in pF for the calculations.
Not Tested.
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
Ensured by the T
T
R
T
T
T
T
HD:DAT
Sym
max.+t
RSCL
RSDA
FSDA
FSCL
IL
I
2
of the falling edge of the SCL signal. This specification is not a part of the I
C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
SU;DAT
Characteristic
Data input hold
SDA rise time
SCL rise time
SCL fall time
SDA fall time
SU;DAT
AA
= 1000 + 250 = 1250 ns (according to the standard-mode I
time
3.4 MHz specification test.
≥ 250 ns must then be met. This will automatically be the case if the device does not
2
C-bus device can be used in a standard-mode (100 kHz) I
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
Operating Voltage V
1.7 MHz mode
1.7 MHz mode
3.4 MHz mode
3.4 MHz mode
1.7 MHz mode
3.4 MHz mode
1.7 MHz mode
3.4 MHz mode
1.7 MHz mode
3.4 MHz mode
1.7 MHz mode
3.4 MHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
DD
range is described in
Min
—
20
20
10
10
20
10
—
20
10
—
20
10
—
0
0
0
0
–40°C ≤ T
(4)
1000
1000
Max
300
160
300
160
300
300
300
300
160
80
40
80
80
80
40
80
—
—
—
—
MCP444X/446X
A
≤ +125°C (Extended)
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC/DC characteristics
2
C bus specification) before
Cb is specified to be from
10 to 400 pF (100 pF maxi-
mum for 3.4 MHz mode)
After a Repeated Start con-
dition or an Acknowledge
bit
After a Repeated Start
condition or an Acknowl-
edge bit
Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
1.8V-5.5V,
2.7V-5.5V,
4.5V-5.5V,
4.5V-5.5V,
2
2
C specification, but
C-bus system, but the
Conditions
DS22265A-page 15
Note 6
Note 6
Note 6
Note 6
IH