MCP4461T-104E/ST Microchip Technology, MCP4461T-104E/ST Datasheet - Page 74

• Manufacturer Part Number: MCP4461T-104E/ST
• Description: IC DGTL POT 257TAPS 100K 20TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP4461T-104E/ST

• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Temperature Coefficient: 150 ppm/°C Typical
• Taps: 257
• Resistance (ohms): 100K
• Number Of Circuits: 4
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Pots: Quad
• Taps Per Pot: 257
• Resistance: 100 KOhms
• Wiper Memory: Non Volatile
• Buffered Wiper: Buffered
• Digital Interface: I2C
• Operating Supply Voltage: 2.7 V to 5.5 V
• Supply Current: 600 uA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Description/function: Quad I2C Digital POT with Nonvolatile Memory
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP444X/446X
8.2
Figure 8-3
the
Disconnecting the wiper allows the transistor input to
be taken to the Bias voltage level (disconnecting A and
or B may be desired to reduce system current).
Disconnecting Terminal A modifies the transistor input
by the R
Disconnecting Terminal B modifies the transistor input
by the R
Common A and Common B connections could be
connected to V
FIGURE 8-3:
using Terminal Disconnects.
DS22265A-page 74
Input
Input
independent
Using Shutdown Modes
AW
BW
shows a possible application circuit where
Balance
rheostat value to the Common A. The
DD
rheostat value to the Common B.
B
A
and V
Common A
Common B
terminals
Example Application Circuit
SS
W
.
Bias
could
To base
of Transistor
(or Amplifier)
be
used.
8.3
At times, it may become necessary to perform a
Software Reset Sequence to ensure the MCP44XX
device is in a correct and known I
This technique only resets the I
This is useful if the MCP44XX device powers up in an
incorrect state (due to excessive bus noise, etc), or if
the Master Device is reset during communication.
Figure 8-4
software reset the device.
FIGURE 8-4:
Format.
The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
Master Device. In this mode, the device is monitoring
the data bus in Receive mode and can detect the Start
bit forces an internal Reset.
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP44XX is driving an A bit on
the I
command) and is driving a data bit of ‘0’ onto the I
bus. In both of these cases, the previous Start bit could
not be generated due to the MCP44XX holding the bus
low. By sending out nine ‘1’ bits, it is ensured that the
device will see a A bit (the Master Device does not drive
the I
MCP44XX), which also forces the MCP44XX to reset.
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the Master
Device was reset while sending a Write command to
the MCP44XX, AND then as the Master Device returns
to normal operation and issues a Start condition while
the MCP44XX is issuing an Acknowledge. In this case,
if the 2nd Start bit is not sent (and the Stop bit was sent)
the MCP44XX could initiate a write cycle.
The Stop bit terminates the current I
MCP44XX waits to detect the next Start condition.
This sequence does not effect any other I
which may be on the bus, as they should disregard this
as an invalid command.
Start
bit
Note:
Note:
S
2
2
C bus low to acknowledge the data sent by the
C bus, or is in output mode (from a Read
‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’
Software Reset Sequence
This technique is documented in AN1028.
shows the communication sequence to
The potential for this erroneous write
ONLY occurs if the Master Device is reset
while sending a Write command to the
MCP44XX.
Nine bits of ‘1’
Software Reset Sequence
© 2010 Microchip Technology Inc.
Stop bit
Start bit
2
C state machine.
2
2
C bus activity. The
C Interface state.
2
S
C devices
P
2
C