XC2V8000-5FF1517I Xilinx Inc, XC2V8000-5FF1517I Datasheet - Page 317

• Manufacturer Part Number: XC2V8000-5FF1517I
• Description: IC FPGA VIRTEX-II 1517FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V8000-5FF1517I

• Number Of Labs/clbs: 11648
• Total Ram Bits: 3096576
• Number Of I /o: 1108
• Number Of Gates: 8000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -

Revision History
This section records the change history for this module of the data sheet.
DS031-4 (v3.5) November 5, 2007
Product Specification
11/07/00
11/22/00
12/19/00
01/25/01
02/07/01
04/02/01
11/07/01
09/26/02
10/07/02
12/06/02
05/07/03
06/19/03
08/01/03
03/29/04
06/24/04
03/01/05
11/05/07
Date
R
Version
1.8.1
1.8.2
1.8.3
2.0.1
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
2.0
3.3
3.4
3.5
Early access draft.
Initial Xilinx release. Made the following corrections:
CS144 package -
•
•
FG256 package -
•
FG896 package -
•
FF1152 package -
•
Reverse designations were fixed for pins in every package.
Data sheet divided into four modules (per current style standard). DXN and DXP pin
information added for CS144 package
DXN and DXP pin information was changed back to RSVD for the CS144 package
and the FG256 package
•
•
•
•
•
•
•
•
•
•
All Virtex-II devices and speed grades now Production. See Table 13, Module 3.
Recompiled for backward compatibility with Acrobat 4 and above.
Added references to, and new package drawings for, Pb-free wire-bond packages CSG,
FGG, and BGG. (Revision number advanced to level of complete data sheet.)
Table
“Input/Output/Bidirectional”. Added requirement to V
if battery is not used.
Updated copyright notice and legal disclaimer.
Added missing pin D10 in Bank 1.
Changed dedicated pins A3 and A4 to RSVD (from DXN and DXP).
Corrected pin AG1 in Bank 4 to be AG12.
Corrected pin Y3 in Bank 6 to be Y32.
ALT_VRN and ALT_VRP pin information was added for each package.
Table 8, page 34
FG676 package.
Reverted to traditional double-column format.
Updated list of devices supported in the FF1152, FF1517, and BF957 packages.
Updated
Added mention of LVPECL to pin definition in
Corrected
Enhanced the description of the PWRDWN_B pin in
Added clarification to
nature of pins D0/DIN and BUSY/DOUT during configuration.
The final GND pin in each of five pinout tables was inadvertently deleted in v1.8.2. This
revision restores the deleted GND pins as follows:
-
-
-
-
-
Changed dedicated pins A2 and B2 to RSVD (from DXN and DXP).
4: Changed Direction for User I/O pins (IO_LXXY_#) from “Input/Output” to
Pin C5,
Pin A1,
Pin A2,
Pin A2,
Pin AL30,
Table 3
Table 10
Table 6, page 10
Table 10, page 72
Table 12, page 120
Table 5, page 5
Table 5, page
Table 6, page
Table 11, page
Table 14, page 198
Table 12, page
to reflect devices supported in the BG728 and BF957 packages.
– added No Connect designations for the XC2V1500 device in the
www.xilinx.com
heading to reflect supported devices in the BG728 package.
(Table
Table 4
6).
5:
10:
(CS144)
94:
(FG256)
and all device pinout tables regarding the dual-use
120:
(BG728)
(FF1152)
(BF957)
(Table
Revision
Virtex-II Platform FPGAs: Pinout Information
5) and FG256 package
Table
BATT
4.
Table
to connect pin to V
4.
(Table
CCAUX
6).
Module 4 of 4
(Table
or GND
5)
225