XC2V8000-5FF1517I Xilinx Inc, XC2V8000-5FF1517I Datasheet - Page 66

• Manufacturer Part Number: XC2V8000-5FF1517I
• Description: IC FPGA VIRTEX-II 1517FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V8000-5FF1517I

• Number Of Labs/clbs: 11648
• Total Ram Bits: 3096576
• Number Of I /o: 1108
• Number Of Gates: 8000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -

Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4" of FR4
microstrip trace. Standard termination was used for all test-
ing. (See
The propagation delay of the 4" trace is characterized sep-
arately and subtracted from the final measurement, and is
therefore not included in the generalized test setup shown in
Figure
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it. (IBIS
models can be found on the web at
inx.com/support/sw_ibis.htm
C
I/O standard. The most accurate prediction of propagation
delay in any given application can be obtained through IBIS
simulation, using the following method:
1. Simulate the output driver of choice into the generalized
2. Record the time to V
3. Simulate the output driver of choice into the actual PCB
Table 19: Output Delay Measurement Methodology
DS031-3 (v3.5) November 5, 2007
Product Specification
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS ), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
HSTL, Class IV
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL, Class IV, 1.8V
REF
test setup, using values from
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
, and V
1.
Virtex-II Platform FPGA User Guide
R
MEAS
fully describe the test conditions for each
Description
MEAS
.) Parameters V
.
Table
19.
http://support.xil-
REF
for details.)
, R
www.xilinx.com
REF
Virtex-II Platform FPGAs: DC and Switching Characteristics
,
PCI33_3 (falling edge)
PCI66_3 (falling edge)
PCI33_3 (rising edge)
PCI66_3 (rising edge)
4. Record the time to V
5. Compare the results of steps 2 and 4. The increase or
PCIX (rising edge)
PCIX (falling edge
IOSTANDARD
HSTL_III_18
HSTL_IV_18
HSTL_II_18
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
HSTL_I_18
decrease in delay should be added to or subtracted
from the I/O Output Standard Adjustment value
(Table
delay (clock-to-input) of the PCB trace.
LVTTL (all)
Attribute
HSTL_IV
HSTL_III
HSTL_II
HSTL_I
GTLP
FPGA Output
GTL
17) to yield the actual worst-case propagation
Figure 1: Generalized Test Setup
V
MEAS
REF
R
(Ω)
1M
1M
1M
1M
R
C
(probe capacitance)
1M
25
25
25
25
25
25
25
25
50
25
25
50
25
50
25
50
REF
.
REF
REF
V
(voltage level at which
delay measurement is taken)
MEAS
C
(pF)
REF
10
10
10
10
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(2)
(2)
(2)
(2)
(3)
(3)
(1)
ds083-3_06a_092503
V
V
V
V
V
1.65
1.25
0.75
0.94
2.03
0.94
2.03
0.94
2.03
MEAS
(V)
0.9
1.1
1.4
0.9
0.8
1.0
0.9
1.1
REF
REF
REF
REF
Module 3 of 4
V
0.75
0.75
(V)
3.3
3.3
3.3
1.2
1.5
1.5
1.5
0.9
0.9
1.8
1.8
REF
0
0
0
0
0
0
0
18