NUC120RD1BN Nuvoton Technology Corporation of America, NUC120RD1BN Datasheet - Page 312

• Manufacturer Part Number: NUC120RD1BN
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC120RD1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Capture Control Register (CCR0)
Register
CCR0
Bits
[31:24]
[23]
[22]
[5]
[20]
[19]
CFLRI1
CFLRI0
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Offset
PWMA_BA+0x50 R/W
PWMB_BA+0x50 R/W
Descriptions
Reserved
CFLRI1
CRLRI1
Reserved
CAPIF1
CAPCH1EN
CRLRI1
CRLRI0
30
22
14
6
Reserved
Reserved
R/W
Reserved
CFLR1 Latched Indicator Bit
When PWM group input channel 1 has a falling transition, CFLR1 was latched with the
value of PWM down-counter and this bit is set by hardware.
In Medium Density, software can write 0 to clear this bit to zero.
In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can
Write 1 to clear this bit to zero if BCn bit is 1.
CRLR1 Latched Indicator Bit
When PWM group input channel 1 has a rising transition, CRLR1 was latched with the
value of PWM down-counter and this bit is set by hardware.
In Medium Density, software can write 0 to clear this bit to zero.
In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can
Write 1 to clear this bit to zero if BCn bit is 1.
Reserved
Channel 1 Capture Interrupt Indication Flag
If PWM group channel 1 rising latch interrupt is enabled (CRL_IE1=1), a rising
transition occurs at PWM group channel 1 will result in CAPIF1 to high; Similarly, a
falling transition will cause CAPIF1 to be set high if PWM group channel 1 falling latch
interrupt is enabled (CFL_IE1=1).
Write 1 to clear this bit to zero
Channel 1 Capture Function Enable
1 = Enable capture function on PWM group channel 1
29
21
13
5
Description
PWM Group A Capture Control Register
PWM Group B Capture Control Register
(Medium Density Only)
CAPIF1
CAPIF0
28
20
12
4
- 312 -
Reserved
Reserved
CAPCH1EN
CAPCH0EN
27
19
11
3
Publication Release Date: Dec. 22, 2010
FL_IE1
FL_IE0
26
18
10
2
RL_IE1
RL_IE0
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
0x0000_0000
INV1
INV0
24
16
8
0