P1021PSE2HFB Freescale Semiconductor, P1021PSE2HFB Datasheet - Page 23

• Manufacturer Part Number: P1021PSE2HFB
• Description: IC MPU 800MHZ 689TEPBGAII
• Manufacturer: Freescale Semiconductor
• Series: QorlQ™r

Specifications of P1021PSE2HFB

• Processor Type: e500
• Speed: 800MHz
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Voltage: -
• Other names: P1021PSE2HFA; P1021PSE2HFA

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Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
P1020/21/22 core can be configured to
fetch boot code from one of the following
I/O interfaces:
Internal Boot ROM allows customer boot
code to be loaded to DRAM from SPI or
SD flash memory
As a PCI agent or PCI Express
P1020/21/22 can also be initialized from
an external host before local boot code is
executed.
I
perform register or memory initialization
by loading data and addresses from I
EEPROM before P1020/21/22 is released
for initial boot code fetch.
2
•
•
•
•
C Boot Sequencer can optionally
Local Bus (8/16/32b port size)
PCI Express
DDR SDRAM
Internal Boot ROM
®
®
endpoint,
2
C
PCIe Boot
Enhanced
SPI Boot
SD Boot
I
Local Bus
Controller
2
C Boot
boot
P1020/21/22 Boot Modes
23
Initialization and Boot
Booting the system using either Parallel NAND
x8, x16, and x32 boot device(s) via the parallel
Support checking/verifying ECC for NAND flash
Boot vector fetch can be routed to the PCI
Device Boot from SPI Flash and 16-bit/24-bit
Supports boot from both SDC and MMC cards
Support for optionally loading configuration data
Support for extended I
Support for checking/verifying ECC during the
flash, Parallel NOR flash, Parallel NVRAM
and battery-backed RAM
address/data bus
boot blocks during the boot process
Express interfaces if external boot ROM is
located on any of those interfaces
address SPI EEPROM (Master mode only)
from serial ROM at reset via the I
interface, which can be used to initialize
configuration registers and/or memory
boot process
2
C addressing mode
2
C
TM