TCS3414CS TAOS, TCS3414CS Datasheet - Page 17

• Manufacturer Part Number: TCS3414CS
• Description: Photodiodes TriColor Sensor RGB, Clear Ch
• Manufacturer: TAOS
• Type: Digital Color Light Sensorr

Specifications of TCS3414CS

• Peak Wavelength: 470 nm
• Maximum Rise Time: 300 ns
• Maximum Fall Time: 300 ns
• Package / Case: Chipscale-6
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ambient Light Sensor
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Interrupt Control Register (02h)
The LUMENOLOGY r Company
Reset Value:
INTR_STOP
PERSIST
PERSIST
The INTERRUPT register controls the extensive interrupt capabilities of the device. The open-drain interrupt
pin is active low and requires a pullup resistor to V
Source Register (03h), the interrupt can be configured to trigger on any one of the four ADC channels. The
TCS3404/14 permits both SMB-Alert style interrupts as well as traditional level style interrupts. The Interrupt
Register provides control over when a meaningful interrupt will occur. The concept of a meaningful change can
be defined by the user both in terms of light intensity and time, or persistence of that change in intensity. The
value must cross the threshold (as configured in the Threshold Registers 08h through 0Bh) and persist for some
period of time as outlined in the table below.
When a level Interrupt is selected, an interrupt is generated whenever the last conversion results in a value
outside of the programmed threshold window. The interrupt is active-low and remains asserted until cleared by
writing an 11 in the TRANSACTION field in the COMMAND register.
In SMB-Alert mode, the interrupt is similar to the traditional level style and the interrupt line is asserted low. To
clear the interrupt, the host responds to the SMB-Alert by performing a modified Receive Byte operation, in
which the Alert Response Address (ARA) is placed in the slave address field, and the TCS3404/14 that
generated the interrupt responds by returning its own address in the seven most significant bits of the receive
data byte. If more than one device connected on the bus has pulled the SMBAlert line low, the highest priority
(lowest address) device will win control of the bus during the slave address transfer. If the device loses this
arbitration, the interrupt will not be cleared. The Alert Response Address is 0Ch.
When INTR = 11, the interrupt is generated immediately following the SMBus write operation. Operation then
behaves in an SMB-Alert mode, and the software set interrupt may be cleared by an SMB-Alert cycle.
FIELD
Resv
INTR
INTR
Resv
02h
Resv
7
0
BITS
5:4
5:4
2:0
2:0
7
6
3
INTR_STOP
Reserved. Write as 0.
Stop ADC integration on interrupt. When high, ADC integration will stop once an interrupt is asserted.
To resume operation (1) de-assert ADC_EN using CONTROL register, (2) clear interrupt using
COMMAND register, and (3) re-assert ADC_EN using CONTROL register. Note: Use this bit to isolate
a particular condition when the sensor is continuously integrating.
INTR Control Select. This field determines mode of interrupt logic according to the table below:
NOTE: Value 11 may be used to test interrupt connectivity in a system or to assist in debugging interrupt
service routine software. See Application Software section for further information.
Reserved. Write as 0.
Interrupt persistence. Controls rate of interrupts to the host processor:
0
6
FIELD VALUE
FIELD VALUE
000
001
010
011
00
01
10
11
Table 6. Interrupt Control Register
5
0
r
INTR
Interrupt output disabled.
Level Interrupt.
SMB-Alert compliant.
Sets an interrupt and functions as mode 10.
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4
0
DD
in order to pull high in the inactive state. Using the Interrupt
0.1 sec
TIMER
Single
Every
1 sec
Resv
3
0
DESCRIPTION
INTERRUPT CONTROL
DIGITAL COLOR LIGHT SENSORS
2
0
Every ADC cycle generates interrupt
Any value outside of threshold range.
Consecutively out of range for 0.1 second
Consecutively out of range for 1 second
r
PERSIST
TCS3404CS, TCS3414CS
1
0
DESCRIPTION
TAOS068 − FEBRUARY 2009
Copyright E 2009, TAOS Inc.
0
0
INTERRUPT
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