TCS3414CS TAOS, TCS3414CS Datasheet - Page 20

• Manufacturer Part Number: TCS3414CS
• Description: Photodiodes TriColor Sensor RGB, Clear Ch
• Manufacturer: TAOS
• Type: Digital Color Light Sensorr

Specifications of TCS3414CS

• Peak Wavelength: 470 nm
• Maximum Rise Time: 300 ns
• Maximum Fall Time: 300 ns
• Package / Case: Chipscale-6
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ambient Light Sensor
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TCS3404CS, TCS3414CS
DIGITAL COLOR LIGHT SENSORS
TAOS068 − FEBRUARY 2009
Interrupt Threshold Register (08h − 0Bh)
NOTES: 1. The Interrupt Source Register (03h) selects which ADC channel to generate an interrupt and should correspond to the threshold
ADC Channel Data Registers (10h − 17h)
NOTE: The SMBus Read Word protocol can be used to read byte-paired registers. For example, the DATA1LOW and DATA1HIGH registers (as
20
Copyright E 2009, TAOS Inc.
The interrupt threshold registers store the values to be used as the high and low trigger points for the comparison
function for interrupt generation. The high and low bytes from each set of registers are combined to form a 16-bit
threshold value. If the value generated by the Interrupt Source Register (03h) converges below or equal to the
low threshold specified, an interrupt is asserted on the interrupt pin. If the value generated by Interrupt Source
Register (03h) converges above the high threshold specified, an interrupt is asserted on the interrupt pin.
Registers LOW_THRESH_LOW_BYTE and LOW_THRESH_HIGH_BYTE provide the low byte and high byte,
respectively,
HIGH_THRESH_HIGH_BYTE provide the low and high bytes, respectively, of the upper interrupt threshold.
The interrupt threshold registers default to 00h on power up.
The ADC channel data are expressed as 16-bit values spread across four registers. The channel low and high
provide the lower and upper bytes respectively for each ADC channel data registers. Each DATALOW and
DATAHIGH register is identified below as 1, 2, 3, or 4. All channel data registers are read-only and default to
00h on power up.
The upper byte data registers can only be read following a read to the corresponding lower byte register. When
the lower byte register is read the upper eight bits are strobed into a shadow register, which is read by a
subsequent read to the upper byte. The upper register will therefore read the correct value even if additional
ADC integration cycles complete between the reading of the lower and upper registers.
well as the other three individual register pairs) may be read together to obtain the 16-bit ADC value in a single transaction.
2. Since two 8-bit values are combined for a single 16-bit value for each of the high and low interrupt thresholds, the SMBus Send Byte
HIGH_THRESH_HIGH_BYTE
LOW_THRESH_HIGH_BYTE
HIGH_THRESH_LOW_BYTE
LOW_THRESH_LOW_BYTE
setting. Both registers should be configured appropriately when setting up an interrupt service routine.
protocol should not be used to write to these registers. Any values transferred by the Send Byte protocol with the MSB set would
be interpreted as the COMMAND field and stored as an address for subsequent read/write operations and not as the interrupt
threshold information as desired. The Write Word protocol should be used to write byte-paired registers. For example, the
LOW_THRESH_LOW_BYTE and LOW_THRESH_HIGH_BYTE registers (as well as the HIGH_THRESH_LOW_BYTE and
HIGH_THRESH_HIGH_BYTE registers) can be written together to set the 16-bit ADC value in a single transaction.
REGISTER
of
GREEN_HIGH
GREEN_LOW
CLEAR_HIGH
CLEAR_LOW
BLUE_HIGH
BLUE_LOW
REGISTER
RED_HIGH
RED_LOW
the
lower
Table 11. ADC Channel Data Registers
Table 10. Interrupt Threshold Register
ADDRESS
interrupt
10h
11h
12h
13h
14h
15h
16h
17h
ADDRESS
r
0Ah
0Bh
08h
09h
www.taosinc.com
threshold.
BITS
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
BITS
7:0
7:0
7:0
7:0
ADC channel 1 lower byte
ADC channel 1 upper byte
ADC channel 2 lower byte
ADC channel 2 upper byte
ADC channel 3 lower byte
ADC channel 3 upper byte
ADC channel 4 lower byte
ADC channel 4 upper byte
ADC interrupt source lower byte of the low threshold.
ADC interrupt source upper byte of the low threshold.
ADC interrupt source lower byte of the high threshold.
ADC interrupt source upper byte of the high threshold.
Registers
DESCRIPTION
r
HIGH_THRESH_LOW_BYTE
DESCRIPTION
The LUMENOLOGY r Company
and