V2DIP1-64 FTDI, V2DIP1-64 Datasheet - Page 16

• Manufacturer Part Number: V2DIP1-64
• Description: Interface Modules & Development Tools USB Vinculum-II 64 Pin Mod 1 USB Port
• Manufacturer: FTDI

Specifications of V2DIP1-64

• Interface Type: USB, Serial, UART, FIFO, SPI
• Data Bus Width: Serial, 8 bit
• Operating Supply Voltage: 5 V
• Product: Interface Modules
• For Use With/related Products: VNC2-64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.6.2 Timing Diagram – Asynchronous FIFO Mode Read and Write Cycle
When in Asynchronous FIFO interface mode, the timing of a read and write operation on the FIFO
interface is shown in Figure 3.3 and Table 3.7
Table 3.7 - Asynchronous FIFO Mode Read Cycle Timing
In asynchronous mode an external device can control data transfer driving FIFO_WR# and FIFO_RD#
inputs. In contrast to synchronous mode, in asynchronous mode the 245 FIFO module generates the
output enable EN# signal. EN# signal is effectively the read signal RD#.
Current byte is available to be read when FIFO_RD# goes low. When FIFO_RD# goes high, FIFO_RXF#
output will also go high. It will only become low again when there is another byte to read.
When FIFO_WR# goes low FIFO_TXE# flag will always go high. FIFO_TXE# goes low again only when
there is still space for data to be written in to the module.
Figure 3.3 – Asynchronous FIFO Mode Read and Write Cycle.
Time
t10
t11
t1
t2
t3
t4
t5
t6
t7
t8
t9
RD# inactive to RXF#
RXF# inactive after RD# cycle
RD# to Data
RD# active pulse width
RD# active after RXF#
WR# active to TXE# inactive
TXE# inactive after WR# cycle
DATA to TXE# active setup time
DATA hold time after WR# inactive
WR# active pulse width
WR# active after TXE#
Description
Copyright © 2010 Future Technology Devices International Limited
V2DIP1-64 VNCL2-64Q Development Module Datasheet Version 1.0
Min
100
100
30
30
1
1
0
1
5
5
0
Max
14
14
14
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document Reference No.: FT_000165
Clearance No.: FTDI# 154
15