WM8776SEFT/V Wolfson Microelectronics, WM8776SEFT/V Datasheet - Page 31

• Manufacturer Part Number: WM8776SEFT/V
• Description: Audio CODECs Stereo CODEC with 5-Ch Mux
• Manufacturer: Wolfson Microelectronics

Specifications of WM8776SEFT/V

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
w
(both channels)
Attenuation
Attenuation
Attenuation
REGISTER
ADDRESS
R3 (03h)
0000011
R4 (04h)
0000100
R5 (05h)
0000101
Master
DACR
Digital
Digital
Digital
DACL
BIT
7:0
7:0
7:0
8
8
8
MASTDA[7:0]
UPDATED
UPDATED
UPDATED
RDA[6:0]
Table 13 Headphone Volume Control Attenuation Levels
In addition a zero cross detect circuit is provided for the output PGA volume under the control of bit 7
(ZCEN) in the each attenuation register. When ZCEN is set the attenuation values are only updated
when the input signal to the gain stage is close to the analogue ground level. This minimises audible
clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which will
generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of
12.288MHz). The timeout clock may be disabled by setting TOD.
DAC DIGITAL VOLUME CONTROL
The DAC volume may also be adjusted in the digital domain using independent digital attenuation
control registers
LDA[7:0]
LABEL
REGISTER ADDRESS
Timeout Clock Disable
HPLA/ HPRA[6:0]
79 (hex)
7D(hex)
7E(hex)
00(hex)
2F(hex)
30(hex)
7F(hex)
R7 (07h)
0000111
:
:
:
Not latched
Not latched
Not latched
DEFAULT
11111111
11111111
11111111
(0dB)
(0dB)
(0dB)
3
BIT
Digital Attenuation data for Left channel DACL in 0.5dB steps. See
Table 14
Controls simultaneous update of Attenuation Latches
Digital Attenuation data for Right channel DACR in 0.5dB steps. See
Table 14
Controls simultaneous update of Attenuation Latches
Digital Attenuation data for DAC channels in 0.5dB steps. See Table
14
Controls simultaneous update of Attenuation Latches
ATTENUATION LEVEL
0dB (default)
-∞dB (mute)
-∞dB (mute)
0: Store LDA in intermediate latch (no change to output)
1: Store LDA and update attenuation on both channels
0: Store RDA in intermediate latch (no change to output)
1: Store RDA and update attenuation on both channels.
0: Store gain in intermediate latch (no change to output)
1: Store gain and update attenuation on channels.
LABEL
TOD
-73dB
+4dB
+5dB
+6dB
:
:
:
DEFAULT
0
DESCRIPTION
DAC and ADC Analogue Zero
cross detect timeout disable
0 : Timeout enabled
1: Timeout disabled
PD, Rev 4.1, September 2008
DESCRIPTION
WM8776
31