A3PN250-ZVQG100 Actel, A3PN250-ZVQG100 Datasheet - Page 31
A3PN250-ZVQG100
Manufacturer Part Number
A3PN250-ZVQG100
Description
FPGA - Field Programmable Gate Array 250K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet
1.A3PN030-ZVQG100.pdf
(106 pages)
Specifications of A3PN250-ZVQG100
Processor Series
A3PN250
Core
IP Core
Number Of Macrocells
2048
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
68
Data Ram Size
36 Kbit
Delay Time
1.05 ns
Supply Voltage (max)
3.3 V
Supply Current
3 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
250 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3PN250-ZVQG100
Manufacturer:
ACT
Quantity:
19
Company:
Part Number:
A3PN250-ZVQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A3PN250-ZVQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 2-16 • Summary of AC Measuring Points
Table 2-17 • I/O AC Parameter Definitions
Standard
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
Parameter
t
t
t
t
t
t
t
t
t
t
t
DP
PY
DOUT
EOUT
DIN
HZ
ZH
LZ
ZL
ZHS
ZLS
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer
Data to Output Buffer delay through the I/O interface
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Enable to Pad delay through the Output Buffer—HIGH to Z
Enable to Pad delay through the Output Buffer—Z to HIGH
Enable to Pad delay through the Output Buffer—LOW to Z
Enable to Pad delay through the Output Buffer—Z to LOW
Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH
Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW
R e v i s i o n 8
Parameter Definition
Measuring Trip Point (Vtrip)
0.90 V
0.75 V
1.4 V
1.4 V
1.2 V
ProASIC3 nano Flash FPGAs
2- 17