A2F200M3F-1FGG256 Actel, A2F200M3F-1FGG256 Datasheet - Page 101

• Manufacturer Part Number: A2F200M3F-1FGG256
• Description: FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
• Manufacturer: Actel

Specifications of A2F200M3F-1FGG256

• Processor Series: A2F200
• Core: ARM Cortex M3
• Number Of Logic Blocks: 8
• Maximum Operating Frequency: 120 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 4608 bit
• Delay Time: 200 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 200000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-99 • I
Figure 2-47 • I2C Timing Parameter Definition
SDA
SCL
Parameter
t
t
Notes:
1. These maximum values are provided for information only. Minimum output buffer resistance values depend on
2. These values are provided for a load of 100 pF and 400 pF. For board design considerations and detailed output buffer
3. For allowable Pclk configurations, refer to the Inter-Integrated Circuit (I
SU;STO
FILT
VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output
buffer resistances, use the corresponding IBIS models located on the SoC Products Group website at
http://www.actel.com/download/ibis/default.aspx.
resistances,
http://www.actel.com/download/ibis/default.aspx.
Microcontroller Subsystem User’s
t
SU;STA
Commercial Case Conditions: T
STOP setup time
Maximum spike width filtered
2
C Characteristics
S
use
t
HD;STA
the
Definition
t
LOW
T
RISE
corresponding
3
t
Guide.
HIGH
t
HD;DAT
T
FALL
IBIS
J
= 85ºC, V
models
t
SU;DAT
DD
R e v i s i o n 6
Condition
located
= 1.425 V, –1 Speed Grade (continued)
–
–
on
SmartFusion Intelligent Mixed Signal FPGAs
2
the
C) Peripherals section in the
SoC
Products
Value
50
1
Group
t
SU;STO
P
SmartFusion
website
pclk cycles
Unit
ns
2- 89
at