A2F200M3F-1FGG256 Actel, A2F200M3F-1FGG256 Datasheet - Page 42

FPGA - Field Programmable Gate Array 200K System Gates SmartFusion

A2F200M3F-1FGG256

Manufacturer Part Number
A2F200M3F-1FGG256
Description
FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
Manufacturer
Actel
Datasheet

Specifications of A2F200M3F-1FGG256

Processor Series
A2F200
Core
ARM Cortex M3
Number Of Logic Blocks
8
Maximum Operating Frequency
120 MHz
Number Of Programmable I/os
117
Data Ram Size
4608 bit
Delay Time
200 ns
Supply Voltage (max)
3.6 V
Supply Current
3 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
200000
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
A2F200M3F-1FGG256
Manufacturer:
ACT
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Manufacturer:
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Part Number:
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Quantity:
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SmartFusion DC and Switching Characteristics
Table 2-34 • Minimum and Maximum DC Input and Output Levels
Table 2-35 • Minimum and Maximum DC Input and Output Levels
Figure 2-6 • AC Loading
Table 2-36 • AC Waveforms, Measuring Points, and Capacitive Loads
2- 30
3.3 V LVTTL /
3.3 V LVCMOS
Drive Strength
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
3.3 V LVTTL /
3.3 V LVCMOS
Drive Strength
8 mA
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Input Low (V)
0
Note:
*Measuring point = V
Applicable to FPGA I/O Banks
Applicable to MSS I/O Banks
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer.
Test Point
Datapath
Min.
–0.3
–0.3
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
V
Input High (V)
VIL
VIL
3.3
Max.
Max.
trip.
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
V
V
See
35 pF
Table 2-21 on page 2-24
Min.
Min.
V
V
2
2
2
2
2
2
2
2
Measuring Point* (V)
VIH
VIH
Max.
Max.
Enable Path
3.6
Test Point
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
V
1.4
R = 1 K
Max.
Max.
VOL
VOL
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
V
V
R e visio n 6
for a complete table of trip points.
VOH
VOH
Min.
Min.
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
R to VCCxxxxIOBx for t
R to GND for t
V
V
35 pF for t
5 pF for t
V
mA mA
mA mA
I
I
24 24
OL
12 12
16 16
OL
2
6
8
REF
4
8
HZ
ZH
I
I
/ t
OH
OH
(typ.) (V)
2
6
8
/ t
4
8
LZ
HZ
ZHS
/ t
ZH
/ t
Max.
Max.
ZL
mA
mA
I
I
109
127
181
/ t
OSL
OSL
27
27
54
54
54
/ t
LZ
ZHS
1
1
ZLS
/ t
ZL
/ t
ZLS
Max.
Max.
I
mA
I
mA
103
132
268
C
OSH
OSH
25
25
51
51
51
LOAD
1
1
35
(pF)
µA
µA
15
15
15
I
I
15
15
15
15
10
IL
IL
2
2
µA
µA
I
15
15
I
15
15
15
15
15
10
IH
IH
2
2

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