AGLP125V5-CSG289 Actel, AGLP125V5-CSG289 Datasheet - Page 11

• Manufacturer Part Number: AGLP125V5-CSG289
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of AGLP125V5-CSG289

• Processor Series: AGLP125
• Core: IP Core
• Number Of Macrocells: 1024
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 4
• Data Ram Size: 4608 bit
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 125 K
• Package / Case: CSP-289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 1-3 • VersaTile Configurations
X1
X2
X3
LUT-3 Equivalent
LUT-3
VersaTiles
The IGLOO PLUS core consists of VersaTiles, which have been enhanced beyond the ProASIC
core tiles. The IGLOO PLUS VersaTile supports the following:
Refer to
User Nonvolatile FlashROM
Actel IGLOO PLUS devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The
FlashROM can be used in diverse system applications:
The FlashROM is written using the standard IGLOO PLUS IEEE 1532 JTAG programming interface. The
core can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks (except in AGLP030 devices), as in security keys
stored in the FlashROM for a user design.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
The Actel IGLOO PLUS development software solutions, Libero
and Designer, have extensive support for the FlashROM. One such feature is auto-generation of
sequential programming files for applications requiring a unique serial number in each part. Another
feature allows the inclusion of static data for system version control. Data for the FlashROM can be
generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive
programming file support is also included to allow for easy programming of large numbers of parts with
differing FlashROM contents.
•
•
•
•
•
•
•
•
•
•
•
•
Y
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
Figure 1-3
for VersaTile configurations.
D-Flip-Flop with Clear or Set
Data
CLK
CLR
D-FF
R ev i si o n 1 1
Y
Enable D-Flip-Flop with Clear or Set
IGLOO PLUS Low Power Flash FPGAs
Enable
®
Integrated Design Environment (IDE)
Data
CLK
CLR
D-FF
Y
PLUS®
1 -5