AGLP125V5-CSG289 Actel, AGLP125V5-CSG289 Datasheet - Page 64

FPGA - Field Programmable Gate Array 125K System Gates

AGLP125V5-CSG289

Manufacturer Part Number
AGLP125V5-CSG289
Description
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer
Actel
Datasheet

Specifications of AGLP125V5-CSG289

Processor Series
AGLP125
Core
IP Core
Number Of Macrocells
1024
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
4
Data Ram Size
4608 bit
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
125 K
Package / Case
CSP-289
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGLP125V5-CSG289I
Quantity:
1 190
IGLOO PLUS DC and Switching Characteristics
Table 2-79 • Output Enable Register Propagation Delays
2- 50
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OECLKQ
OESUD
OEHD
OECLR2Q
OEPRE2Q
OEREMCLR
OERECCLR
OEREMPRE
OERECPRE
OEWCLR
OEWPRE
OECKMPWH
OECKMPWL
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
Clock Minimum Pulse Width High for the Output Enable Register
Clock Minimum Pulse Width Low for the Output Enable Register
1.2 V DC Core Voltage
J
= 70°C, Worst-Case VCC = 1.14 V
Description
R ev i sio n 1 1
Table 2-7 on page 2-7
for derating values.
1.06
0.52
0.00
1.25
1.36
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
Std. Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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