AGLP125V5-CSG289 Actel, AGLP125V5-CSG289 Datasheet - Page 52

• Manufacturer Part Number: AGLP125V5-CSG289
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of AGLP125V5-CSG289

• Processor Series: AGLP125
• Core: IP Core
• Number Of Macrocells: 1024
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 4
• Data Ram Size: 4608 bit
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 125 K
• Package / Case: CSP-289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO PLUS DC and Switching Characteristics
Table 2-64 • Minimum and Maximum DC Input and Output Levels
Figure 2-11 • AC Loading
Table 2-65 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-66 • 1.2 V LVCMOS Low Slew
Table 2-67 • 1.2 V LVCMOS High Slew
2- 38
1.2 V
LVCMOS
Drive
Strength
2 mA
Notes:
1. Applicable to IGLOO nano V2 devices operating at VCCI ≥ VCC.
2. I
3. I
4. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
Input Low (V)
0
*
Drive Strength
2 mA
Note:
Drive Strength
2 mA
Notes:
1. For specific junction temperature and voltage supply levels, refer to
2. Software default selection highlighted in gray.
Measuring point = Vtrip. See
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
For specific junction temperature and voltage supply levels, refer to
1
Min.
Commercial-Case Conditions: T
Commercial-Case Conditions: T
–0.3 0.35 * VCCI 0.65 * VCCI
1.2 V LVCMOS (JESD8-12A)
Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V
applications. It uses a 1.2 V input buffer and a push-pull output buffer.
Timing Characteristics
V
Applies to 1.2 V DC Core Voltage
Test Point
Datapath
V
Speed Grade
Speed Grade
IL
Max.
V
STD
STD
Table 2-23 on page 2-21
5 pF
Min.
Input High (V)
V
t
t
DOUT
0.98
DOUT
0.98
V
IH
1.2
Max.
8.27 0.19 1.57
3.38 0.19 1.57
Enable Path
J
J
t
t
3.6
Test Point
DP
DP
V
= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
R = 1 k
t
t
0.25 * VCCI 0.75 * VCCI 2
DIN
DIN
for a complete table of trip points.
Max.
R ev i sio n 1 1
V
V
OL
t
t
PY
PY
Measuring Point* (V)
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
t
2.34
t
2.34
PYS
PYS
Table 2-6 on page 2-6
Min.
V
0.6
V
OH
Table 2-6 on page 2-6
t
t
EOUT
0.67
EOUT
0.67
HZ
ZH
mA mA
/ t
I
OL
/ t
LZ
HZ
LZ
7.94 6.77
3.26 2.78
ZHS
t
t
ZL
ZL
I
OH
/ t
/ t
2
ZH
ZL
/ t
for derating values.
ZL
t
t
/ t
Max.
mA
/ t
ZH
ZH
I
OSL
20
ZLS
/ t
ZHS
4
ZLS
3.00
2.99 3.24
for derating values.
C
t
t
LZ
LZ
LOAD
Max.
I
mA
OSH
26
5
3.11
t
t
(pF)
4
HZ
HZ
µA
I
IL
10 10
Units
Units
2
5
ns
ns
µA
I
IH
3
5