AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 193

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-99 • Minimum and Maximum DC Input and Output Levels
Figure 2-117 • AC Loading
3.3 V LVTTL /
3.3 V LVCMOS
Drive Strength
Applicable to Pro I/O Banks
4 mA
8 mA
12 mA
16 mA
24 mA
Applicable to Advanced I/O Banks
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Applicable to Standard I/O Banks
2 mA
4 mA
6 mA
8 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is
supported as part of the 3.3 V LVTTL support.
Data Path
Test Point
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
VIL
Max.
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
V
35 pF
Min.
V
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
VIH
Enable Path
Test Point
Max.
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
R = 1 k
R e v i s i o n 1
Max.
VOL
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
V
VOH
Min.
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
V
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
mA mA
I
12
16
24
12
16
24
OL
4
8
2
4
6
8
2
4
6
8
Actel Fusion Family of Mixed Signal FPGAs
HZ
ZH
I
12
16
24
12
16
24
OH
4
8
2
4
6
8
2
4
6
8
/ t
/ t
LZ
HZ
LZ
ZHS
Max.
mA
I
/ t
/ t
109
127
181
109
127
181
OSL
27
54
27
27
54
54
27
27
54
54
ZH
ZL
/ t
3
ZL
/ t
/ t
ZLS
/ t
ZHS
ZLS
Max.
I
mA
103
132
268
103
132
268
OSH
25
51
25
25
51
51
25
25
51
51
3
µA
I
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
IL
1
4
2- 177
µA
I
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
IH
2
4